Información de la conferencia

CODES+ISSS 2026: International Conference on Hardware/Software Codesign and System Synthesis

Día de Entrega:
2026-03-23 Cerrado
Fecha de Notificación:
2026-07-17
Fecha de conferencia:
2026-10-04
Ubicación:
Barcelona, Spain
Ediciones:
24
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CCF: B   QUALIS: A2   Vistas: 82562   Seguidores: 56   Asistentes: 7
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Índice Conference Partner (CP-I)

72,4 / 100
Puesto n.º 307 de 5.776 congresos · 6% superior

N.º 40 de 249 en Ingeniería de software

Reconocimiento académico (35%)
92
Selectividad en la revisión (20%) Sin datos: se puntúa con la línea base neutra de 50 —
Ediciones celebradas (20%)
87
Atención de la comunidad (10%)
54
Integridad del registro público (15%)
50

Datos utilizados: Categorías: CCF B, QUALIS A2 · Ediciones documentadas: 24 · Investigadores que lo siguen aquí: 56 · Investigadores que abrieron esta página en los últimos 24 meses: 6

Falta en el registro público: Tasas de aceptación históricas (+4,5) · Ediciones anteriores (+3,0)
Los organizadores pueden añadirlo desde esta página tras reclamar el congreso; las puntuaciones se recalculan cada noche. Cómo subir esta puntuación

Confianza 80 %: la parte de la puntuación respaldada por datos observados y no por la línea base neutra. Cómo se calcula esta puntuación · Ver la clasificación · Versión del algoritmo 1.2 · Calculado el 2026-11-12

Investigadores de estas instituciones siguen este congreso

Huazhong University of Science and Technology 9
Peking University 4
Shandong University 4
Institute of Information Engineering, Chinese Academy of Sciences 3
University of Science and Technology of China 3

Según la institución que cada investigador indica en su perfil. No la verificamos.

Solicitud de Artículos

CODES+ISSS 2026 (International Conference on Hardware/Software Codesign and System Synthesis) is a CCF B / QUALIS A2 conference held in Barcelona, Spain on 2026-10-04. The paper submission deadline is 2026-03-23. Acceptance notifications are sent on 2026-07-17.

The IEEE/ACM International Conference on Codesign of Embedded Systems (CODES) is the premier conference in system-level design, hardware/software co-design, modeling, analysis, and implementation of modern embedded systems, cyber-physical systems, and internet-of-things, from system-level specification and optimization to synthesis of system-on-chip hardware/software implementations. CODES is part of Embedded Systems Week (ESWEEK), the premier event covering all aspects of hardware and software design for smart, intelligent, and connected computing systems. Journal-Integrated Publication Model: All full papers accepted in EMSOFT’25 will be published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). All late-breaking papers accepted in one of the three conferences will be published in IEEE Embedded Systems Letters (ESL). See details at http://esweek.org/author-information In-Person Presentation Requirement: An accepted paper will be removed from the journal (TCAD or ESL) and the technical program unless both of the following conditions are satisfied: (1) One author of the accepted paper must register at the full conference (author registration) rate, and (2) An author of the accepted paper must present (in-person) the paper in the conference. See details at http://esweek.org/author-information Topics of Interests Track 1) System-level design – Specification, modelling, refinement, synthesis, and partitioning of embedded systems, hardware-software co-design, hybrid system modeling and design, model-based design, design for adaptivity and reconfigurability. Track 2) Application-specific design – Analysis, design, and optimization techniques for multimedia, medical, automotive, transportation, cyber-physical, aerospace, IoT, space computing and other application domains. Track 3) System architecture – Heterogeneous systems, many-cores, and distributed systems, architecture and micro-architecture design, exploration and optimizations of application-specific processors and accelerators, reconfigurable, self-programmable, and self-adaptive architectures, storage, memory systems, networks-on-chip, and networks-of-networks. Track 4) Simulation, validation, and verification – Hardware/software co-simulation, verification and validation methodologies, formal verification, hardware accelerated simulation, simulation and verification languages, models, and benchmarks. Track 5) Embedded software – Language and library support, compilers, runtimes, parallelization, software verification, memory management, virtual machines, operating systems, real-time support, middleware. Track 6) Safety, security, and reliability – Cross-layer reliability, resiliency and fault tolerance, test methodology, design for security, reliability, and testability, hardware security, security for embedded, CPS, and IoT devices. Track 7) Power-aware systems – Power-aware, thermal-aware and energy-aware system design and methodologies, ranging from low-power embedded and cyber-physical systems, IoT devices, to energy-efficient large-scale systems such as cloud datacenters, federated systems, green computing, and smart grids. Track 8) Embedded artificial intelligence – Hardware and software design, implementation, and optimization for machine learning that are specially designed for resource- and power-constrained embedded, CPS, and IoT devices. Track 9) Industrial practices and case studies – Practical impact on current and/or future industries, application of state-of-the-art methodologies and tools in wireless, networking, multimedia, automotive, cyber-physical, IoT, aerospace, space computing, federated systems, etc.
Última actualización por Dou Sun el

Los Mejores Artículos

AñoLos Mejores Artículos
2019Transaction level modeling: an overview
2019Achieving Lossless Accuracy with Lossy Programming for Efficient Neural-Network Training on NVM-Based Systems
2018XNOR Neural Engine: a Hardware Accelerator IP for 21.6 fJ/op Binary Neural Network Inference
2017Flexible PV-cell modeling for energy harvesting in wearable IoT applications
2016A Design to Reduce Write Amplification in Object-based NAND Flash Devices
2015R2Cache: Reliability-Aware Reconfigurable Last-Level Cache Architecture for Multi-Cores
2014TSP: Thermal Safe Power - Efficient power budgeting for Many-Core Systems in Dark Silicon
2013Improving Polyhedral Code Generation for High-Level Synthesis
2012A Traffic-Aware Adaptive Routing Algorithm on a Highly Reconfigurable Network-on-Chip Architecture
2011Reliable Software for Unreliable Hardware: Embedded Code Generation aiming at Reliability
2010Worst-case Performance Analysis of Synchronous Dataflow Scenarios
2009A standby-sparing technique with low energy-overhead for fault-tolerant hard real-time systems
2008Hardware/Software Partitioning of Floating Point Software Applications to Fixed-Point Coprocessor Circuits
2007Dynamic security domain scaling on symmetric multiprocessors for future high-end embedded systems
2006Architectural support for safe software execution on embedded processors
2005A unified approach to constrained mapping and routing on network-on-chip architectures
2004Parallel programming models for a multi-processor SoC platform applied to high-speed traffic management
2003An efficient retargetable framework for instruction-set simulation

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