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FPGA 2027: International Symposium on Field-Programmable Gate Arrays

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투고 마감일:
2026-10-01
통보일:
2026-11-24
개최일:
2027-03-14
개최지:
Seaside, California, USA
개최 횟수:
CCF: B   ICORE: A   QUALIS: A2   조회: 69044   팔로우: 72   참가: 7

회반 지수 (CP-I)

78.5 / 100
전체 5,693개 중 220위 · 상위 4%

시스템·아키텍처 분야 341개 중 44위

학술적 인정 (35%)
92
투고 선별성 (20%) 데이터 없음 — 중립 기준값 50점으로 계산 —
개최 횟수 (20%)
96
커뮤니티 관심도 (10%)
65
공개 자료 충실도 (15%)
70

사용한 입력: 수록 등급: CCF B, ICORE A, QUALIS A2 · 확인되는 개최 횟수: 35 · 회반에서 팔로우 중인 연구자: 72명 · 지난 24개월 동안 이 페이지를 연 연구자: 23명

공개 자료에서 빠진 항목: 역대 게재율 (+4.5)
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신뢰도 80% — 점수 중 중립 기준값이 아니라 실제 관측된 데이터에 근거한 비율. 이 점수는 어떻게 계산되나 · 전체 순위 보기 · 알고리즘 버전 1.1 · 산출일 2026-10-03

논문 모집

FPGA 2027 (International Symposium on Field-Programmable Gate Arrays) is a CCF B / ICORE A / QUALIS A2 conference held in Seaside, California, USA on 2027-03-14. The paper submission deadline is 2026-10-01. Acceptance notifications are sent on 2026-11-24.

The ACM/SIGDA International Symposium on Field-Programmable Gate Arrays is the premier conference for the presentation of advances in FPGA technology. In March 2027, the 35th edition of ISFPGA will be held in California, USA. Accepted papers will be published in the conference proceedings and available in the ACM Digital Library. Submission Topics FPGA’s scope includes spatial architectures more broadly, including coarse-grained reconfigurable arrays (CGRAs), neural processing units (NPUs), AI Engines, and other dataflow/spatial computing fabrics, alongside our core FPGA focus. We solicit research papers in the following topic areas: FPGA and Spatial Architecture Design: Architectures for programmable logic fabrics, CGRAs, NPUs, AI Engines, and other spatial compute fabrics, including routing/interconnect, reconfigurable logic or processing elements, embedded blocks (memory, DSP, processors), and I/O interfaces. Novel commercial and open-source architectures and architectural features. FPGA Circuit Design: Circuits and layout techniques for the design of FPGAs and spatial fabrics. Impacts of future process and design technologies on FPGAs as well as novel memory or nanoscale devices. Methods for analyzing and improving static and dynamic power consumption, power and clock distribution, yield, manufacturability, security, reliability, and testability. CAD for FPGAs and Spatial Architectures: Algorithms for synthesis, technology mapping, logic and timing optimization, clustering, placement, and routing on FPGAs as well as scheduling/mapping for spatial and dataflow architectures. Novel design software for system-level partitioning, debug, and verification. Algorithms for modeling, analysis, and optimization of timing and power. High-Level Abstractions and Tools: General-purpose and domain-specific languages, tools, and techniques to facilitate the design, debugging, or verification of applications targeting FPGAs and spatial architectures. Novel hardware/software co-design and high-level synthesis methodologies enabling mapping of specialized applications onto FPGAs and spatial architectures. FPGA-based and FPGA-like Computing Engines: Systems and software for compiled accelerators on spatial computing engines/NPUs or programmable overlay architectures implemented using FPGAs. Applications and Design Studies: Implementation of novel designs on FPGAs or spatial architectures establishing state-of-the-art in high-performance, low-power, security, or high-reliability. Designs leveraging unique capabilities of these architectures or demonstrating significant improvements over alternative programmable technologies (e.g., CPU, GPU). Design studies and architecture explorations enabling CAD and architecture improvements. AI/ML for and on FPGAs and Spatial Architectures: FPGA-based accelerators for AI/ML algorithms, such as Large Language Models and World Models and implementations on spatial architectures. Novel uses of AI models to aid in the design and programming of FPGAs.
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