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FPGA 2027: International Symposium on Field-Programmable Gate Arrays

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截稿日期:
2026-10-01 还有 13 天
通知日期:
2026-11-24
会议日期:
2027-03-14
会议地点:
Seaside, California, USA
届数:
CCF: B   ICORE: A   QUALIS: A2   浏览: 68442   关注: 72   参加: 7

会伴指数 (CP-I)

78.3 / 100
全站第 218 名 / 共 5,682 个会议 · 前 4%

系统与体系结构 第 44 / 341

学术认可 (35%)
92
投稿选择性 (20%) 无数据 —— 按中性基准 50 分计入 —
会议传承 (20%)
96
社区关注 (10%)
63
资料公开度 (15%)
70

用到的输入: 收录等级：CCF B, ICORE A, QUALIS A2 · 有据可查的届次：35 · 在会伴关注它的研究者：72 人 · 过去 24 个月打开过本页的研究者：16 人

公开资料里还缺: 历年录用率 (+4.5)
主办方认领本会议后，可直接在这一页补上；分数每晚重算。如何提升这个分数

置信度 80% —— 分数中有多大比例来自实际观测到的数据，而不是中性基准。 这个分数是怎么算出来的 · 查看完整榜单 · 算法版本 1.1 · 算于 2026-09-17

征稿

FPGA 2027 (International Symposium on Field-Programmable Gate Arrays) is a CCF B / ICORE A / QUALIS A2 conference held in Seaside, California, USA on 2027-03-14. The paper submission deadline is 2026-10-01. Acceptance notifications are sent on 2026-11-24.

The ACM/SIGDA International Symposium on Field-Programmable Gate Arrays is the premier conference for the presentation of advances in FPGA technology. In March 2027, the 35th edition of ISFPGA will be held in California, USA. Accepted papers will be published in the conference proceedings and available in the ACM Digital Library. Submission Topics FPGA’s scope includes spatial architectures more broadly, including coarse-grained reconfigurable arrays (CGRAs), neural processing units (NPUs), AI Engines, and other dataflow/spatial computing fabrics, alongside our core FPGA focus. We solicit research papers in the following topic areas: FPGA and Spatial Architecture Design: Architectures for programmable logic fabrics, CGRAs, NPUs, AI Engines, and other spatial compute fabrics, including routing/interconnect, reconfigurable logic or processing elements, embedded blocks (memory, DSP, processors), and I/O interfaces. Novel commercial and open-source architectures and architectural features. FPGA Circuit Design: Circuits and layout techniques for the design of FPGAs and spatial fabrics. Impacts of future process and design technologies on FPGAs as well as novel memory or nanoscale devices. Methods for analyzing and improving static and dynamic power consumption, power and clock distribution, yield, manufacturability, security, reliability, and testability. CAD for FPGAs and Spatial Architectures: Algorithms for synthesis, technology mapping, logic and timing optimization, clustering, placement, and routing on FPGAs as well as scheduling/mapping for spatial and dataflow architectures. Novel design software for system-level partitioning, debug, and verification. Algorithms for modeling, analysis, and optimization of timing and power. High-Level Abstractions and Tools: General-purpose and domain-specific languages, tools, and techniques to facilitate the design, debugging, or verification of applications targeting FPGAs and spatial architectures. Novel hardware/software co-design and high-level synthesis methodologies enabling mapping of specialized applications onto FPGAs and spatial architectures. FPGA-based and FPGA-like Computing Engines: Systems and software for compiled accelerators on spatial computing engines/NPUs or programmable overlay architectures implemented using FPGAs. Applications and Design Studies: Implementation of novel designs on FPGAs or spatial architectures establishing state-of-the-art in high-performance, low-power, security, or high-reliability. Designs leveraging unique capabilities of these architectures or demonstrating significant improvements over alternative programmable technologies (e.g., CPU, GPU). Design studies and architecture explorations enabling CAD and architecture improvements. AI/ML for and on FPGAs and Spatial Architectures: FPGA-based accelerators for AI/ML algorithms, such as Large Language Models and World Models and implementations on spatial architectures. Novel uses of AI models to aid in the design and programming of FPGAs.
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