会議情報

FPGA 2027: International Symposium on Field-Programmable Gate Arrays

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投稿締切日:
2026-10-01
通知日:
2026-11-24
開催日:
2027-03-14
開催地:
Seaside, California, USA
開催回数:
CCF: B   ICORE: A   QUALIS: A2   閲覧: 69043   フォロー: 72   参加: 7

会伴インデックス (CP-I)

78.5 / 100
全 5,693 件中 第 220 位 · 上位 4%

システム・アーキテクチャ 分野 341 件中 第 44 位

学術的評価 (35%)
92
投稿の選択性 (20%) データなし — 中立の基準値 50 点として算入 —
開催回数 (20%)
96
コミュニティの注目度 (10%)
65
公開情報の充実度 (15%)
70

使用した入力: 収録ランク:CCF B, ICORE A, QUALIS A2 · 確認できる開催回数:35 · 会伴でフォローしている研究者:72 人 · 過去 24 か月にこのページを開いた研究者:23 人

公開情報で不足しているもの: 過去の採択率 (+4.5)
主催者は会議を認証申請したうえで、このページから直接追加できます。スコアは毎晩再計算されます。このスコアを上げるには

信頼度 80% — スコアのうち、中立の基準値ではなく実際に観測されたデータに基づく割合。 このスコアの算出方法 · ランキングを見る · アルゴリズム版 1.1 · 算出日 2026-10-02

論文募集

FPGA 2027 (International Symposium on Field-Programmable Gate Arrays) is a CCF B / ICORE A / QUALIS A2 conference held in Seaside, California, USA on 2027-03-14. The paper submission deadline is 2026-10-01. Acceptance notifications are sent on 2026-11-24.

The ACM/SIGDA International Symposium on Field-Programmable Gate Arrays is the premier conference for the presentation of advances in FPGA technology. In March 2027, the 35th edition of ISFPGA will be held in California, USA. Accepted papers will be published in the conference proceedings and available in the ACM Digital Library. Submission Topics FPGA’s scope includes spatial architectures more broadly, including coarse-grained reconfigurable arrays (CGRAs), neural processing units (NPUs), AI Engines, and other dataflow/spatial computing fabrics, alongside our core FPGA focus. We solicit research papers in the following topic areas: FPGA and Spatial Architecture Design: Architectures for programmable logic fabrics, CGRAs, NPUs, AI Engines, and other spatial compute fabrics, including routing/interconnect, reconfigurable logic or processing elements, embedded blocks (memory, DSP, processors), and I/O interfaces. Novel commercial and open-source architectures and architectural features. FPGA Circuit Design: Circuits and layout techniques for the design of FPGAs and spatial fabrics. Impacts of future process and design technologies on FPGAs as well as novel memory or nanoscale devices. Methods for analyzing and improving static and dynamic power consumption, power and clock distribution, yield, manufacturability, security, reliability, and testability. CAD for FPGAs and Spatial Architectures: Algorithms for synthesis, technology mapping, logic and timing optimization, clustering, placement, and routing on FPGAs as well as scheduling/mapping for spatial and dataflow architectures. Novel design software for system-level partitioning, debug, and verification. Algorithms for modeling, analysis, and optimization of timing and power. High-Level Abstractions and Tools: General-purpose and domain-specific languages, tools, and techniques to facilitate the design, debugging, or verification of applications targeting FPGAs and spatial architectures. Novel hardware/software co-design and high-level synthesis methodologies enabling mapping of specialized applications onto FPGAs and spatial architectures. FPGA-based and FPGA-like Computing Engines: Systems and software for compiled accelerators on spatial computing engines/NPUs or programmable overlay architectures implemented using FPGAs. Applications and Design Studies: Implementation of novel designs on FPGAs or spatial architectures establishing state-of-the-art in high-performance, low-power, security, or high-reliability. Designs leveraging unique capabilities of these architectures or demonstrating significant improvements over alternative programmable technologies (e.g., CPU, GPU). Design studies and architecture explorations enabling CAD and architecture improvements. AI/ML for and on FPGAs and Spatial Architectures: FPGA-based accelerators for AI/ML algorithms, such as Large Language Models and World Models and implementations on spatial architectures. Novel uses of AI models to aid in the design and programming of FPGAs.
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