会议信息

HiPEAC 2027: International Conference on High Performance and Embedded Architectures and Compilers

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HiPEAC
截稿日期:
2026-06-01
通知日期:
会议日期:
2027-01-18
会议地点:
Glasgow, Scotland, UK
届数:
22
CCF: B   QUALIS: B2   浏览: 47421   关注: 55   参加: 3

征稿

HiPEAC 2027 (International Conference on High Performance and Embedded Architectures and Compilers) is a CCF B / QUALIS B2 conference held in Glasgow, Scotland, UK on 2027-01-18. The paper submission deadline is 2026-06-01.

HiPEAC has been pioneering the journal-first publication model. Journal-first means that the manuscript selection process for the conference is outsourced to a journal (ACM TACO). Manuscripts can be submitted to the journal at any time throughout the year as regular journal submissions. For all manuscripts submitted before June 1, 2026, ACM TACO guarantees that the final decision (including two rounds of revision) will be communicated before November 15. All authors of original work papers accepted in the journal between November 15, 2025 and November 15, 2026 will get an invitation to present their work during the paper track of the HiPEAC conference. There are no conference proceedings published. Topics of interest include, but are not limited to: Processor, memory, and storage systems architecture Parallel, multi-core and heterogeneous systems Interconnection networks Architectural support for programming productivity Power, performance and implementation efficient designs Reliability and real-time support in processors, compilers and run-time systems Application-specific processors, accelerators and reconfigurable processors Architecture and programming environments for GPU-based computing Simulation and methodology Architectural and run-time support for programming languages Programming models, frameworks and environments for exploiting parallelism Compiler techniques Feedback-directed optimization Program characterization and analysis techniques Dynamic compilation, adaptive execution, and continuous profiling/optimization Binary translation/optimization Code size/memory footprint optimizations
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