Conference Information
CASES 2022: International Conference on Compilers, Architectures, and Synthesis for Embedded Systemsing
https://esweek.org/cases/
Submission Date:
2022-03-31
Notification Date:
2022-07-05
Conference Date:
2022-10-07
Location:
Shanghai, China
Years:
17
CCF: c   CORE: a   QUALIS: a2   Viewed: 23417   Tracked: 33   Attend: 5

Call For Papers
CASES 2022 solicits the submission of original research articles in two categories, i) full-length research papers that will be published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), and ii) short Work-in-Progress papers that will be published in the CASES Proceedings. For both categories, CASES solicits submission on the following topics divided into five technical tracks. Each submission needs to specify one primary and one secondary track based on the relevance of the paper’s technical content to the tracks. This year’s theme is AI at the edge. More information about the submission is at https://www.esweek.org/author-information.

Topics of Interests

Track 1: AI Systems and Applications of AI at Edge
Artificial Intelligence of Things (IoT), Edge intelligence, Architectures, accelerators, and compilers for artificial intelligence hardware; Applications of machine learning algorithms and techniques to embedded systems, IoT, and Cyber-Physical Systems (CPS); Neuromorphic and cognitive computing, analytics for embedded applications; and validation techniques for AI components.

Track 2: Embedded Systems and IoT/CPS Security, Safety, Reliability, and Energy-Efficiency
Secure architectures, hardware security, software security for embedded systems, IoT, and CPS; Architecture, design, and compiler techniques for energy efficiency, reliability, and aging; Modeling, analysis, and optimization for timing and predictability; Validation, verification, testing, and debugging of embedded software.

Track 3: Memory and Storage
Memory system architecture; Persistent memory, Emerging memory technologies (e.g., ReRAM, MRAM, FeRAM, DNA); Caches, scratchpad memory, and com-piler-controlled memory; Reconfigurable memory; Pro-cessing-in-memory; and storage systems.

Track 4: Accelerators, Emerging Technologies, and Applications
Synthesis, optimization, and design-space exploration of high-performance, low-power accelerators; Domain-specific accelerators; Compilers for accelerators; Biologically-inspired computing; Heterogeneous and domain-specific multi-core SoC; Approximate computing; Flexible, stretchable, and flexible hybrid electronics (FHE); Augmented/virtual reality.

Track 5: Architectures, Compilers, System-level Design
Embedded and mobile processor micro-architecture, Multi- and many-core processors, GPU architectures, Reconfigurable computing including FPGAs and CGRAs for embedded systems and IoT/CPS, Application-Specific processor design, 3D-stacked architectures; Networks-on-Chip (NoC) architectures; on-chip communication; I/O management in embedded systems; and compiler support for CPU, GPU, reconfigurable computing, compilation for memory, storage, and on-chip communications.
Last updated by Dou Sun in 2022-03-06
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