CASES 2026 (International Conference on Compilers, Architectures, and Synthesis for Embedded Systemsing) is a CCF C / QUALIS A2 conference held in Barcelona, Spain on 2026-10-04. The paper submission deadline is 2026-03-23. Acceptance notifications are sent on 2026-07-17.
CASES is a premier forum, where researchers, developers, and practitioners exchange information on the latest advances in design, optimization, validation, and applications of embedded systems, Internet of Things (IoT), and the emergent trend of integrating Artificial Intelligence into IoT (AIoT). The conference has a long tradition of showcasing cutting-edge research in these broad areas, covering topics including, but not limited to, hardware-software co-design and co-validation, edge AI, embedded architecture, compilers for heterogeneous systems, memory/storage technology, security/reliability, energy-efficiency of embedded systems, and domain-specific hardware accelerators.
CASES 2026 solicits the submission of original research articles for full-length research papers that will be published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). CASES solicits submissions on the following topics divided into five technical tracks. Page length and formatting details are available on the author information page.
Topics of Interests
Track 1: AI Systems and Applications of AI at Edge
Artificial Intelligence of Things (IoT), Edge intelligence, Architectures, accelerators, and compilers for artificial intelligence hardware; Applications of machine learning algorithms and techniques to embedded systems, IoT, and Cyber-Physical Systems (CPS); Neuromorphic and cognitive computing, analytics for embedded applications; and validation techniques for AI components.
Track 2: Embedded Systems and IoT/CPS Security, Safety, Reliability, and Energy-Efficiency
Secure architectures, hardware security, software security for embedded systems, IoT, and CPS; Architecture, design, and compiler techniques for energy efficiency, reliability, and aging; Modeling, analysis, and optimization for timing and predictability; Validation, verification, testing, and debugging of embedded software.
Track 3: Memory and Storage
Memory system architecture; Persistent memory, Emerging memory technologies (e.g., ReRAM, MRAM, FeRAM, DNA); Caches, scratchpad memory, and compiler-controlled memory; Reconfigurable memory; Processing-in-memory; and storage systems.
Track 4: Accelerators, Emerging Technologies, and Applications
Synthesis, optimization, and design-space exploration of high-performance, low-power accelerators; Domain-specific accelerators; Compilers for accelerators; Biologically-inspired computing; Heterogeneous and domain-specific multi-core SoC; Approximate computing; Flexible, stretchable, and flexible hybrid electronics (FHE); Augmented/virtual reality.
Track 5: Architectures, Compilers, System-level Design
Embedded and mobile processor micro-architecture, Multi- and many-core processors, GPU architectures, Reconfigurable computing including FPGAs and CGRAs for embedded systems and IoT/CPS, Application-Specific processor design, 3D-stacked architectures; Networks-on-Chip (NoC) architectures; on-chip communication; I/O management in embedded systems; and compiler support for CPU, GPU, reconfigurable computing, compilation for memory, storage, and on-chip communications.
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