Conference Information
ICCD 2020: International Conference on Computer Design
Submission Date:
2020-06-12 Extended
Notification Date:
Conference Date:
Hartford, Connecticut, USA
CCF: b   QUALIS: a2   Viewed: 20005   Tracked: 82   Attend: 5

Conference Location
Call For Papers
The IEEE International Conference on Computer Design encompasses a wide range of topics in the research, design, and implementation of computer systems and their components. ICCD’s multi-disciplinary emphasis provides an ideal environment for developers and researchers to discuss practical and theoretical work covering systems and applications, computer architecture, verification and test, design tools and methodologies, circuit design, and technology. We especially encourage submissions that look forward to future systems and technologies.
Original manuscripts are welcomed to be submitted to the following tracks:
Track 1. Computer Systems: Systems architecture (memory hierarchy, memory, storage, NoC), and systems software (compiler, programming language/model, OS, hypervisor, runtime) design and co-design for embedded/real-time systems, high-performance computing (HPC) systems, data center and cloud/edge servers, exascale systems; General purpose multi/many cores, co-processors, accelerators, and application-specific systems; Support for security, reliability, and energy efficiency and proportionality; Architectures and compilers for thread parallelism, synchronization, and communication; Virtual memory; Systems support for NVMs and future novel computing platforms including quantum, neuromorphic, and bio-inspired computing; Specialized OS, runtime, and storage systems for high-performance computing and exascale systems.
Track 2. Electronic Design Automation: System-level design and synthesis; High-level, logic and physical synthesis; Physical planning, design, and early estimation for large circuits; Automatic analysis and optimization of timing, power, variability/yield, temperature, and noise; Physical design, including floorplanning, placement, and routing; Clock-tree synthesis; Verification methods at different levels of the EDA flow; Tools for multiple-clock domains, asynchronous, and mixed timing methodologies; CAD support for FPGAs, ASSPs, structured ASICs, platform-based design and NOC; DfM and OPC methodologies; Tools and design methods for emerging technologies (MEMs, spintronics, nano, quantum).
Track 3. Smart, Autonomous and Embedded Systems: Embedded devices and systems; Autonomous systems modeling, sensing, reasoning and computation; Smart systems including smart homes, smart cities, connected communities, smart transportation, smart grid; Perception mechanisms including visual, auditory, and tactile information processing, Neural Computing; Low-power edge and IoT devices: sensing, networking; knowledge acquisition, representation, processing and usage in complex systems; Cyber-physical and Cyber-biological systems
Track 4. Logic and Circuit Design: Circuits and design techniques for digital, memory, analog and mixed-signal systems; Circuits and design techniques for high performance and low power; Circuits and design techniques for robustness under process variability, electromigration, and radiation; Design techniques for emerging and maturing technologies (MEMs, nano-spintronics, quantum, flexible electronics, multigate devices, in-memory computing); Asynchronous circuit design; Signal-processing, graphic-processor, and datapath circuits.
Track 5. Processor Architecture: Microarchitecture design techniques for single- and multi-core processors, such as instruction-level parallelism, pipelining, caching, branch prediction, and multithreading; Techniques for low-power, secure, and reliable processors; Embedded, network, graphic, system-on-chip, application-specific and digital signal processor design; Hardware support for processor virtualization; Real-life design challenges: case studies, tradeoffs, postmortems.
Track 6. Test, Verification, and Security: Design error debug and diagnosis; Fault modeling; Fault simulation and ATPG; Analog/RF testing; Statistical test methods; Large volume yield analysis and learning; Fault tolerance; DFT and BIST; Functional, transaction-level, RTL, and gate-level modeling and verification of hardware designs; Equivalence checking, property checking, and theorem proving; Constrained-random test generation; High-level design and SoC validation; Hardware security primitives; Side-channel analysis; Logic and microarchitectural countermeasures; Hardware security for IoT; Interaction between VLSI test and trust.
Last updated by Dou Sun in 2020-06-07
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