会议信息

PACT 2026: International Conference on Parallel Architectures and Compilation Techniques

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截稿日期:
2026-04-17
通知日期:
2026-08-05
会议日期:
2026-10-19
会议地点:
Chicago, Illinois, USA
届数:
35
CCF: B   ICORE: B   QUALIS: A2   浏览: 74644   关注: 87   参加: 7

会伴指数 (CP-I)

88.2 / 100
全站第 92 名 / 共 5,683 个会议 · 前 2%

软件工程 第 12 / 247 系统与体系结构 第 23 / 341

学术认可 (35%)
92
投稿选择性 (20%)
90
会议传承 (20%)
96
社区关注 (10%)
67
资料公开度 (15%)
80

用到的输入: 收录等级：CCF B, ICORE B, QUALIS A2 · 录用率：20.5%（有记录的 5 届的均值） · 有据可查的届次：35 · 在会伴关注它的研究者：87 人 · 过去 24 个月打开过本页的研究者：24 人

公开资料里还缺: 历届信息 (+3.0)
主办方认领本会议后，可直接在这一页补上；分数每晚重算。如何提升这个分数

置信度 100% —— 分数中有多大比例来自实际观测到的数据，而不是中性基准。 这个分数是怎么算出来的 · 查看完整榜单 · 算法版本 1.1 · 算于 2026-09-21

征稿

PACT 2026 (International Conference on Parallel Architectures and Compilation Techniques) is a CCF B / ICORE B / QUALIS A2 conference held in Chicago, Illinois, USA on 2026-10-19. The paper submission deadline is 2026-04-17. Acceptance notifications are sent on 2026-08-05.

Scope The International Conference on Parallel Architectures and Compilation Techniques (PACT) is a unique technical conference at the intersection of hardware and software, with a special emphasis on parallelism. PACT brings together researchers from computer architectures, compilers, execution environments, programming languages, and applications to present and discuss their latest research results, tools, and practical experiences. This year, PACT is specifically committed to pioneering AI-centric computing, seeking research that redefines the performance, scalability, and efficiency of large-scale AI workloads across diverse parallel and heterogeneous platforms. PACT 2026 will be held as an in-person event in Chicago, IL. USA. We encourage all authors of accepted papers to participate, and at least one author must attend the conference. PACT seeks submissions in two categories: Research Papers Tools and Practical Experience (TPE) Papers Topics of Interest PACT welcomes submissions on topics including, but not limited to: Parallel architectures, including accelerators for AI and other domains Conventional parallel architectures (e.g., multicore, multithreaded, superscalar, and VLIW architectures) and heterogeneous architectures AI accelerators: design of specialized hardware for LLM inference and training (e.g., TPUs, NPUs, and custom silicon) In-memory & near-data processing: architectures to mitigate the “memory wall” in massive AI model parameters Heterogeneous systems: integration of CPUs, GPUs, and FPGAs for distributed AI workloads Scalable AI Infrastructure: Architecture support for multi-node, multi-GPU clusters and high-speed interconnects for LLM scaling Compilers and tools for parallel architectures Conventional compilers and tools for parallel and heterogeneous architectures Dynamic translation and optimization ML compilers: automated optimization, kernel fusion, and code generation for ML frameworks LLMs for compilation: using AI to automate parallelization, loop transformations, and autotuning Dynamic optimization: runtime systems for adaptive AI model execution and sparse computation Quantization & compression: compiler-assisted techniques for model pruning and low-precision arithmetic Middleware and runtime system support for parallel computing Resource management & scheduling Communication & synchronization Energy-aware middleware Quantum-HPC interfacing Serverless parallel computing (e.g., AWS Lambda) AI & LLM-specific runtime support, including distributed inference & training, KV cache management, and computation-communication overlap I/O issues in parallel computing and their application impact Data loading & preprocessing pipelines Metadata scalability Memory-storage convergence Large-scale data processing for AI models and applications Hardware and software resilience & fault tolerance Checkpointing & restart Silent data corruption detection Self-healing runtimes Applications and experimental studies of parallel processing, especially using AI models Parallel programming languages, algorithms, and applications Computational models for concurrent execution Compiler and hardware support for parallel applications Support for correctness in hardware and software Reconfigurable parallel computing Research Papers Research papers will be evaluated by the PACT Program Committee based on: Relevance: The paper should align with PACT’s topics of interest. Novelty/Originality: The work should present new ideas or offer fresh perspectives. Significance: The research should address an important problem and have the potential to influence future work. Results: The claims should be well-supported by clear and validated results. Comparison to Prior Work: The paper should properly discuss existing literature, highlighting similarities, differences, and improvements. Tools and Practical Experience (TPE) Papers TPE papers focus on practical applications, industry challenges, and experience reports. A TPE paper must clearly explain its functionality, summarize practical experience with realistic case studies, and describe any supporting artifacts. The title of a TPE paper must include the prefix “TPE:”. TPE papers follow the same submission guidelines and are reviewed by the same Program Committee as research papers. TPE papers will be evaluated based on: Originality: They should present PACT-related technologies applied to real-world problems. Usability: The tool or software should have broad applicability and aid PACT-related research. Documentation: The tool/software should be well-documented on a public website. Benchmark Repository: A benchmark suite should be provided for testing. Availability: Preference is given to tools/software that are freely available, though industry/commercial tools may be considered with justification. Foundations: The paper should relate to PACT’s principles, though extensive theoretical discussion is not required.
由 Dou Sun 最后更新于

录用率

平均录用率: 22.9% 7 年间 (1999–2005).

年份提交数录用数录用率(%)
20051193025.2%
20041222318.9%
20031442416.7%
20021192521%
20011262620.6%
20001072927.1%
19991143530.7%

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