Conference Information

DATE 2026: Design, Automation and Test in Europe

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Submission Date:
2025-09-15
Notification Date:
2025-11-19
Conference Date:
2026-04-20
Location:
Verona, Italy
Years:
29
CCF: b   CORE: b   QUALIS: a1   Viewed: 948637   Tracked: 152   Attend: 24

Call For Papers

DATE 2026 (Design, Automation and Test in Europe) is a CCF B / CORE B / QUALIS A1 conference held in Verona, Italy on 2026-04-20. The paper submission deadline is 2025-09-15. Acceptance notifications are sent on 2025-11-19.

Topic Areas for Submission Within the scope of the conference, the main areas of interest are organised in the following tracks. Submissions can be made to any of the track topics. Track D: Design Methods and Tools, addresses design automation, design tools and hardware architectures for electronic and embedded systems. The emphasis is on methods, algorithms, and tools related to the use of computers in designing complete systems. The track focus includes significant improvements on existing design methods and tools as well as forward-looking approaches to model and design future system architectures, design flows, and environments. This track is organised in the following topics: D1 System-level design methodologies and high-level synthesis, Click here for details D2 System simulation and validation, Click here for details D3 Formal methods and verification, Click here for details DT4 Design and test for analog and mixed-signal circuits and systems, and MEMS, Click here for details DT5 Design and test of hardware security primitives, Click here for details DT6 Design and test of secure systems, Click here for details D7 Network on chip and on-chip communication, Click here for details D8 Architectural and microarchitectural design, Click here for details D9 Low-power, energy-efficient and thermal-aware design, Click here for details D10 Approximate computing, Click here for details D11 Reconfigurable systems, Click here for details D12 Logical analysis and design, Click here for details D13 Physical analysis and design, Click here for details D14 Emerging design technologies for future computing, Click here for details D15 Emerging design technologies for future memories, Click here for details D16 Design Automation for Quantum Computing, Click here for details Track A: Application Design, is devoted to the presentation and discussion of design experiences with a high degree of industrial relevance, real-world implementations, and applications of specific design and test methodologies. Contributions should illustrate innovative or record-breaking design and test methodologies, which will provide viable solutions in tomorrow’s silicon, embedded systems, and large-scale systems. This track is organised in the following topics: A1 Power-efficiency and Smart Energy Systems for Sustainable Computing, Click here for details A2 Smart Society and Digital Wellness, Click here for details A3 Secure Systems, Circuits and Architectures, Click here for details A4 Autonomous Systems and Smart Industry, Click here for details A5 Applications of Emerging Technologies, Click here for details A6 Applications of Artificial Intelligence Systems, Click here for details Track T: Test and Dependability, covers all test, design-for-test, reliability, and design-for-robustness issues, at system-, chip-, circuit-, and device-level for both analogue and digital electronics. Topics of interest also include diagnosis, failure mode analysis, debug and post-silicon validation challenges, and test or fault injection methods addressing system security. This track is organised in the following topics: T1 Modeling and mitigation of defects, faults, variability, and reliability, Click here for details T2 Test generation, test architectures, design for test, and diagnosis, Click here for details T3 Dependability and system-level test, Click here for details DT4 Design and test for analog and mixed-signal circuits and systems, and MEMS, Click here for details DT5 Design and test of hardware security primitives, Click here for details DT6 Design and test of secure systems, Click here for details Track E: Embedded Systems Design, is devoted to the modelling, analysis, design, verification and deployment of embedded software or embedded/cyber-physical systems. Areas of interest include methods, tools, methodologies and development environments for real-time systems, cyber-physical systems, networked systems, and dependable systems. Emphasis is, also, on model-based design and verification, embedded software platforms, software compilation and integration for these systems. This track is organised in the following topics: E1 Embedded software architecture, compilers and tool chains, Click here for details E2 Real-time, dependable and privacy-enhanced systems, Click here for details E3 Machine learning solutions for embedded and cyber-physical systems, Click here for details E4 Design methodologies for machine learning architectures, Click here for details E5 Design, specification, modeling and verification for embedded and cyber-physical systems, Click here for details
Last updated by Dou Sun in

Acceptance Ratio

Average acceptance rate: 26.7% over 2 years (2005–2006).

YearSubmittedAcceptedAccepted(%)
200683426732%
200582517621.3%

Best Papers

YearBest Papers
2020Statistical Time-based Intrusion Detection in Embedded Systems
2020DEFCON: Generating and Detecting Failure-prone Instruction Sequences via Stochastic Search
2020A Flexible and Scalable NTT Hardware: Applications from Homomorphically Encrypted Deep Learning to Post-Quantum Cryptography
2020Impact of Magnetic Coupling and Density on STT-MRAM Performance
2019When Capacitors Attack: Formal Method Driven Design and Detection of Charge-Domain Trojans
2019Enhancing Reliability of STT-MRAM Caches by Eliminating Read Disturbance Accumulation
2019Error-Shielded Register Renaming Subsystem for a Dynamically Scheduled Out-of-Order Core
2019Data Subsetting: A Data-Centric Approach to Approximate Computing
2018Efficient Verification Of Multi-Property Designs (The Benefit Of Wrong Assumptions)
2018MATIC: Learning Around Errors for Efficient Low-Voltage Neural Network Accelerators
2018Low-Cost High-Accuracy Variation Characterization for Nanoscale IC Technologies via Novel Learning-based Techniques
2018Buffer-aware bounds to multi-point progressive blocking in priority-preemptive NoCs
2017Fast and Waveform-Accurate Hazard-Aware SAT-Based TSOF ATPG
2017CoSyn: Efficient Single-Cell Analysis Using a Hybrid Microfluidic Platform
2017MoDNN: Local Distributed Mobile Computing System for Deep Neural Network
2017Automatic Place-and-Route of Emerging LED-Driven Wires within a Monolithically-Integrated CMOS+III-V Process
2016UTILIZING MACROMODELS IN FLOATING RANDOM WALK BASED CAPACITANCE
2016OTEM: OPTIMIZED THERMAL AND ENERGY MANAGEMENT FOR HYBRID ELECTRICAL ENERGY STORAGE IN ELECTRIC VEHICLES
2016MODELING FABRICATION NON-UNIFORMITY IN CHIP-SCALE SILICON PHOTONIC INTERCONNECTS
2016PROBABILISTIC WCET ESTIMATION IN PRESENCE OF HARDWARE FOR MITIGATING THE IMPACT OF PERMANENT FAULTS
2015HARDWARE TROJAN DETECTION FOR GATE-LEVEL ICS USING SIGNAL CORRELATION BASED CLUSTERING
2015DIGITAL CIRCUITS RELIABILITY WITH IN-SITU MONITORS IN 28NM FULLY DEPLETED SOI
2015PHASE-NOC: TDM SCHEDULING AT THE VIRTUAL-CHANNEL LEVEL FOR EFFICIENT NETWORK TRAFFIC ISOLATION
2009Analysis and optimization of NBTI induced clock skew in gated clock trees
2009On linewidth-based yield analysis for nanometer lithography
2009Gate sizing for large cell-based designs
2008Power Balanced Gates Insensitive to Routing Capacitance Mismatch
2008Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set
2008Analysis and Optimization of the Recessed Probe Launch for High Frequency Measurements of PCB Interconnects
2008Retargetable Code Optimization for Predicated Execution
2007Compositional specification of behavioral semantics
2007Statistical blockade: a novel method for very fast Monte Carlo simulation of rare circuit events, and its application
2006A dynamically reconfigurable packet-switched network-on-chip
2006Optimizing sequential cycles through Shannon decomposition and retiming
2006An effective technique for minimizing the cost of processor software-based diagnosis in SoCs
2005Systematic Transaction Level Modeling of Embedded Systems with SystemC
2005Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices
2005An Application-Specific Design Methodology for STbus Crossbar Generation
2005Design Optimization of Time-and Cost-Constrained Fault-Tolerant Distributed Embedded Systems
2004Wrapper Design for Testing IP Cores with Multiple Clock Domains
2004Automatic Synthesis and Simulation of Continuous-Time [Sigma-Delta] Modulators
2004Poor Mans TBR: A Simple Model Reduction Scheme
2004Digital Ground Bounce Reduction by Phase Modulation of the Clock
2003Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
2003Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step
2003Validating SAT Solvers Using an Independent Resolution-Based Checker: Practical Implementations and Other Applications
2002Analysis of Nonlinearities in RF Front-End Architectures Using a Modified Volterra Series Approach
2002Using Problem Symmetry in Search Based Satisfiability Algorithms
2002Reducing Test Application Time Through Test Data Mutation Encoding
2001Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding
2001SystemCSV - an extension of SystemC for mixed multi-level communication modeling and interface-based system design
2001Probabilistic application modeling for system-level perfromance analysis
2000Cost Reduction and Evaluation of a Temporary Faults Detecting Technique
2000Techniques for Reducing Read Latency of Core Bus Wrappers
2000Code Selection for Media Processors with SIMD Instructions
1999A CAD Framework for Generating Self-Checking 1 Multipliers Based on Residue Codes
1999Symbolic Functional Vector Generation for VHDL Specifications
1998Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays
1998Reduced-Order Modeling of Large Linear Passive Multi-Terminal Circuits Using Matrix-Pade Approximation

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