Conference Information
VTS 2020: VLSI Test Symposium
http://tttc-vts.org
Submission Date:
2019-10-18 Extended
Notification Date:
2019-12-10
Conference Date:
2020-04-05
Location:
San Diego, California, USA
Years:
38
CCF: c   QUALIS: a2   Viewed: 7986   Tracked: 10   Attend: 0

Conference Location
Call For Papers
The VTS Program Committee invites original, unpublished paper submissions for VTS 2020. Proposals for the innovative practices and special sessions tracks are also invited. Paper submissions should be complete manuscripts, up to six pages (inclusive of figures, tables, and bibliography) in a standard IEEE two-column format; papers exceeding the page limit will be returned without review. Authors should clearly explain the significance of the work, highlight novel features, and describe its current status. On the title page, please include: author name(s) and affiliation(s), and the mailing address, phone number, and e-mail address of the contact author. A 50-word abstract and five keywords identifying the topic area are also required.

VTS 2020 will present a Best Paper Award, a Best Special Session Award, and a Best Innovative Practices Session Award based on the evaluations of reviewers, attendees, and an invited panel of judges. We also plan to organize various Student Activities including the TTTC Best Doctoral Thesis Contest, details for which will be made available through the website.

VTS Topics

    Analog/Mixed-Signal/RF Test
    ATPG & Compression
    Silicon Debug
    Automotive Test & Safety
    Built-In Self-Test (BIST)
    Defect & Current Based Test
    Defect/Fault Tolerance
    Delay & Performance Test
    Design for Testability (DFT)
    Design Verification/Validation
    Embedded System & Board Test
    Embedded Test Methods
    Emerging Technologies Test
    FPGA Test
    Fault Modeling and Simulation
    Hardware Security
    Low-Power IC Test
    Microsystems/MEMS/Sensors Test
    Memory Test and Repair
    On-Line Test & Error Correction
    Power/Thermal Issues in Test
    System-on-Chip (SOC) Test
    Test Standards & Economics
    Test of Biomedical Devices
    Test of High-Speed I/O
    Test Quality and Reliability
    Test Resource Partitioning
    Transients and Soft Errors
    2.5D, 3D and SiP Test
    Yield Optimization
Last updated by Dou Sun in 2019-10-12
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