Conference Information
VTS 2026: VLSI Test Symposium
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Submission Date:
2025-11-03
Notification Date:
2026-01-31
Conference Date:
2026-04-27
Location:
Napa, California, USA
Years:
44
CCF: c   QUALIS: a2   Viewed: 31339   Tracked: 21   Attend: 2

Call For Papers
The program includes keynotes, scientific paper presentations, short industrial application paper presentations, special sessions, and Innovative Practices sessions.

You are invited to participate and submit your contributions to VTS’26. The areas of interest include (but are not limited to) the following topics:

VTS Topics

Generative AI Applications in Test and Security
Silicon Lifecycle Management
Silent Data Corruption
Test-Enabled Digital Twin
Analog – Mixed-Signal – RF Test
ATPG and Compression
Automotive Test and Safety
Built-In Self-Test (BIST)
Functional safety
Digital twin-enabled test and security
High BW Test through High-Speed Interfaces
Testing for extreme environments
Test og Non-Si and Compound Circuits
Test and Security of Quantum Circuits
Test and Security of Photonic Circuits
Test and Security of Emerging Memory Technologies
Functional Debug through Scan
Fault Modeling and Simulation
Low-Power IC Test
Machine Learning for Test and Security
Microsystems/MEMS/Sensors Test
Memory Test and Repair
Test for 3D and Heterogenous Integration
Yield Optimization
Online Test and Error Correction
Power and Thermal Issues in Test
System-on-Chip (SOC) Test
Test and Reliability of Biomedical Devices
Test and Reliability of High-Speed I/O
Test and Security of Machine Learning Hardware
Test Standards
FPGA Test
Defect-Based Test
Defect and Fault Tolerance
Delay and Performance Test
Design for Testability
Post-silicon Validation and Debug
Hardware Security
Embedded System and Board Test
Last updated by Dou Sun in 2025-09-16
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