Conference Information

VDAT 2026: International Symposium on VLSI Design and Test

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Submission Date:
2026-04-30
Notification Date:
2026-06-30
Conference Date:
2026-08-20
Location:
Noida, Uttar Pradesh, India
Years:
30
Viewed: 1216   Tracked: 0   Attend: 0

Conference Partner Index (CP-I)

52.6 / 100
Ranked #1,126 of 5,693 conferences · Top 20%

#133 of 341 in Systems & Architecture

Academic recognition (35%) No data - scored at the neutral baseline of 50 —
Submission selectivity (20%) No data - scored at the neutral baseline of 50 —
Editions held (20%)
92
Community attention (10%)
13
Public record completeness (15%)
35

Inputs used: Editions on record: 30 · Researchers who opened this page in the past 24 months: 5

Missing from the public record: Historical acceptance rates (+4.5) · Past editions (+3.0) · Best-paper records (+2.3)
Organizers can add these from this page after claiming the conference; scores are recomputed nightly. How to raise this score

Confidence 45% - the share of the score backed by observed data rather than the neutral baseline. How this score is calculated · Browse the ranking · Algorithm version 1.1 · Computed 2026-10-04

Call For Papers

VDAT 2026 (International Symposium on VLSI Design and Test) is an academic conference held in Noida, Uttar Pradesh, India on 2026-08-20. The paper submission deadline is 2026-04-30. Acceptance notifications are sent on 2026-06-30.

Conference Tracks Track 1 : VLSI & System-on-Chip (SoC) Design Digital, Analog & Mixed-Signal Design Low-Power & High-Performance Architectures Heterogeneous SoC Integration Embedded & Real-Time Systems Memory Subsystems & On-Chip Interconnects Track 2 : Nanoelectronics, Emerging Devices & Beyond-CMOS Technologies FinFET, GAA, Nanosheet & Advanced Transistor Structures 2D Materials & Novel Semiconductor Devices Spintronics & Neuromorphic Devices Device Modeling & Reliability Cryogenic & Advanced Device Technologies Track 3 : Electronic Design Automation (EDA), CAD & AI-Driven Design Physical Design & Place-and-Route Design Space Exploration AI/ML for EDA & Automation Statistical & Formal Verification Design Automation for Advanced Technology Nodes Track 4 : Design Automation for Advanced Technology Nodes Hardware Accelerators for Deep Learning Edge AI & Low-Power AI Systems In-Memory & Near-Memory Computing for AI AI for Semiconductor Manufacturing & Yield Efficient Architectures for LLMs & Emerging AI Models Track 5 : Verification, Testing, Reliability & Hardware Security Design-for-Testability (DFT) & Built-In Self-Test (BIST) Hardware Trust & Security Architectures Fault Tolerance & Resilient Systems Aging, Variability & Radiation Effects Secure SoC & Cryptographic Hardware Track 6 : 3D-IC, Advanced Packaging & Heterogeneous Integration 2.5D/3D IC Integration Chiplets & System-in-Package Thermal & Power Integrity in 3D Systems Advanced Interconnect & TSV Technologies Packaging Solutions for AI & High-Performance Systems Track 7 : Quantum & Future Computing Architectures Quantum Computing Devices & Architectures Quantum Circuit Design & Error Correction Cryogenic CMOS for Quantum Systems A Beyond-CMOS Computing Paradigms Hybrid Classical–Quantum Architectures
Last updated by Dou Sun on

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