Conference Tracks

Track 1 : VLSI & System-on-Chip (SoC) Design
Digital, Analog & Mixed-Signal Design
Low-Power & High-Performance Architectures
Heterogeneous SoC Integration
Embedded & Real-Time Systems
Memory Subsystems & On-Chip Interconnects

Track 2 : Nanoelectronics, Emerging Devices & Beyond-CMOS Technologies
FinFET, GAA, Nanosheet & Advanced Transistor Structures
2D Materials & Novel Semiconductor Devices
Spintronics & Neuromorphic Devices
Device Modeling & Reliability
Cryogenic & Advanced Device Technologies

Track 3 : Electronic Design Automation (EDA), CAD & AI-Driven Design
Physical Design & Place-and-Route
Design Space Exploration
AI/ML for EDA & Automation
Statistical & Formal Verification
Design Automation for Advanced Technology Nodes

Track 4 : Design Automation for Advanced Technology Nodes
Hardware Accelerators for Deep Learning
Edge AI & Low-Power AI Systems
In-Memory & Near-Memory Computing for AI
AI for Semiconductor Manufacturing & Yield
Efficient Architectures for LLMs & Emerging AI Models

Track 5 : Verification, Testing, Reliability & Hardware Security
Design-for-Testability (DFT) & Built-In Self-Test (BIST)
Hardware Trust & Security Architectures
Fault Tolerance & Resilient Systems
Aging, Variability & Radiation Effects
Secure SoC & Cryptographic Hardware

Track 6 : 3D-IC, Advanced Packaging & Heterogeneous Integration
2.5D/3D IC Integration
Chiplets & System-in-Package
Thermal & Power Integrity in 3D Systems
Advanced Interconnect & TSV Technologies
Packaging Solutions for AI & High-Performance Systems

Track 7 : Quantum & Future Computing Architectures
Quantum Computing Devices & Architectures
Quantum Circuit Design & Error Correction
Cryogenic CMOS for Quantum Systems
A Beyond-CMOS Computing Paradigms
Hybrid Classical–Quantum Architectures