Journal Information
IEEE Transactions on Computers (TC)
https://www.computer.org/csdl/journal/tc
Impact Factor:
3.131
Publisher:
IEEE
ISSN:
0018-9340
Viewed:
15610
Tracked:
63

Call For Papers
The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field. It publishes papers, brief contributions, and comments on research in areas of current interest to the readers. These areas include, but are not limited to

    computer organizations and architectures
    operating systems, software systems, and communication protocols
    real-time systems and embedded systems
    digital devices, computer components, and interconnection networks
    specification, design, prototyping, and testing methods and tools
    performance, fault tolerance, reliability, security, and testability
    case studies and experimental and theoretical evaluations
    new and important applications and trends
Last updated by Dou Sun in 2020-05-07
Special Issues
Special Issue on Highlights of Computer Architecture
Submission Date: 2020-06-15

IEEE Transactions on Computers seeks original manuscripts for a special issue on Highlights of Computer Architecture (HiCA). The special issue provides the top-quality journal venue for scientists and engineers to present their latest research findings in this rapidly changing field. Authors of computer architecture conferences in the past 12 months, including but not limited to HPCA 2020, ISCA 2019, and MICRO 2019, are encouraged to submit extended versions of their papers. All aspects of computer architecture are within the scope of this special issue. Topics of interest include, but are not limited to: Accelerators Architecture applications of machine learning Caches Cloud, datacenter, cluster/distributed systems Embedded, IoT Emerging technologies FPGAs and reconfigurable GPUs Hardware/software interactions/interface ILP techniques (speculation, prediction, prefetching, etc.) IO, storage Memory – high level (VM/TLB, persistency, etc.) Memory – low level (devices, organization, etc.) Networking, interconnects Parallel/multi-core architectures Performance characterization/modeling Power efficiency and management Quantum architectures Reliability and fault tolerance Security Submission Guidelines Submitted papers must include new, significant, research-based technical contributions in the scope of the journal. Papers under review elsewhere are not acceptable for submission. Extended versions of published conference papers, including, but not limited to, HPCA2020, ISCA2019, and MICRO2019, are welcome, but there must be at least 40% new impacting technical/scientific material in the journal version and there should be less than 50% verbatim similarity level as reported by a tool (such as CrossRef). The submission must also include the original conference paper with a detailed summary of differences. Submit your paper through ScholarOne and select the Hi-CA special-issue option. As per TC policies, only full-length papers (12+ pages) can be submitted to the special issue (no brief contributions will be considered), and each author’s bio must not exceed 150 words. Papers that are not accepted into the special issue will be considered for a TC regular issue. Important Dates Submission Deadline: June 15, 2020 Reviews Completed: August 15, 2020 Minor Revisions Due: August 31, 2020 Reviews of Revisions Completed: September 15, 2020 Notification of Final Acceptance: September 22, 2020 Publication Materials for Final Manuscripts Due: September 30, 2020 Publication: November 2020 Questions? Please address all correspondence regarding this special issue to Lead Guest Editor Yan Solihin at yan.solihin@ucf.edu. Guest Editors Yan Solihin Director of Cyber Security & Privacy Cluster, Charles N. Milican Professor University of Central Florida Jun Yang Professor, ECE University of Pittsburgh Corresponding Topical Editor (CTE) Avinash Karanth Professor, EECS Ohio University
Last updated by Dou Sun in 2020-05-07
Special Issue on Communications for Many-Core Processors and Accelerators
Submission Date: 2020-07-15

Communications in various forms have become increasingly important with the advent of diverse computing platforms, such as many-core CPUs, GPUs, FPGAs, machine learning (ML) accelerators, and other domain-specific processors. Meanwhile, data-intensive workloads pose greater challenges to both on-chip and off-chip communications, whereas emerging technologies offer new opportunities for interconnection networks. These trends on architecture, application, and technology require innovative communication designs for the next generation of computing systems. This special issue of IEEE Transactions on Computers will explore academic and industrial research on all topics related to the communication issues in general-purpose and domain-specific processors. Topics of interest to this special issue include, but not limited to: Communication architecture for ML accelerators and other app/domain-specific processors Network interface designs for intra/inter-chip and rack-scale networks Security, reliability, and scalability of communications On-chip network architecture and implementation for CPUs, GPUs, and FPGAs Emerging interconnect technologies, such as optical, wireless, CNT, and 2.5D/3D New design methodologies (including ML-based) for communications Communication modeling/characterization, benchmarking, simulation, and verification Communications at un-core level, e.g., interactions with memory controllers, caches, and storages Communications at large scale (data center, edge, and fog computing) Co-optimizations of communications with OS, compilers, and programming models Submitted articles must not have been previously published or currently submitted for journal publication elsewhere. Extended versions of published conference papers (to be included as part of the submission together with a summary of differences) are welcome, but they must have at least 40% new impacting technical/scientific material in the submitted journal version, and there should be less than 50% verbatim similarity as reported by a tool (such as CrossRef). Of note, authors are responsible for understanding and adhering to the TC submission guidelines. Papers should be submitted via ScholarOne Manuscripts by selecting the special-issue option. As per TC policies, only full-length papers (at least 12 pages and according to TC submission requirements) can be submitted to this special issue, and each author’s bio should not exceed 150 words. Please note the following important dates: Submission Deadline: July 15, 2020 Reviews Completed: September 1, 2020 Major Revisions Due: October 1, 2020 Reviews of Revisions Completed: October 15, 2020 Notification of Final Acceptance: November 1, 2020 Publication Materials for Final Manuscripts Due: November 15, 2020 Publication: January 2021 Please address all correspondence regarding this special issue to the guest editors: Lizhong Chen School of EECS, Oregon State University chenliz@oregonstate.edu Zhonghai Lu KTH Royal Institute of Technology zhonghai@kth.se Corresponding Topical Editor Cristina Silvano Politecnico di Milano cristina.silvano@polimi.it
Last updated by Dou Sun in 2020-05-07
Special Issue on Smart Edge Computing and IoT
Submission Date: 2020-08-30

The evolution of the Internet of Things (IoT) is changing the nature of edge-computing devices. End nodes have to support, in place, an increasing range of functionality: multi-sensory data processing and analysis, complex systems control strategies, and, ultimately, artificial intelligence. These new capabilities will enable disruptive innovation in wearable and implantable biomedical devices, autonomous insect-sized drones, autonomous smart environmental sensing, safety-critical real-time applications and structural health monitoring, and more. For this special issue, we are seeking contributions on IoT smart edge-computing architectures, systems, and related hardware-software design approaches. Topics of interest include, but are not limited to: Hardware-software design approaches for smart edge processing Heterogeneous systems-on-chip and architecture for energy-efficient smart edge processing Low-power analog and mixed signal computing, in-memory computing, and in-sensor computing Edge machine-learning architectures dealing with sensor and signal variabilities Neuro-symbolic and brain- and bio-inspired computing paradigms for edge processing IO and peripherals for energy-efficient interfaces in edge-computing systems Edge processing for biomedical IoT systems and human-machine interaction Smart edge IoT devices for structural health monitoring and predictive maintenance Real-time and safety-critical smart edge sensors for industrial IoT Submitted papers must include new significant research-based technical contributions in the scope of the journal. Papers under review elsewhere are not acceptable for submission. Extended versions of published conference papers (to be included as part of the submission together with a summary of differences) are welcome, but they must have at least 40% new impacting technical/scientific material in the submitted journal version, and there should be less than 50% verbatim similarity as reported by a tool (such as CrossRef). Guidelines concerning the submission process and LaTeX and Word templates can be found here. While submitting through ScholarOne, please select this special-issue option. As per TC policies, only full-length papers (at least 12 pages and according to TC submission requirements) can be submitted to special issues, and each author’s bio should not exceed 150 words. Please note the following important dates: Submission Deadline: August 30, 2020 Reviews Completed: October 25, 2020 Major Revisions Due: November 30, 2020 Reviews of Revisions Completed: December 15, 2020 Notification of Final Acceptance: January 1, 2021 Publication Materials for Final Manuscripts Due: January 15, 2021 Publication: March 2021 Please address all correspondence regarding this special issue to Lead Guest Editor Luca Benini (lbenini@iis.ee.ethz.ch). Guest Editors Luca Benini ETH Zürich, Università di Bologna lbenini@iis.ee.ethz.ch Taekwang Jang ETH Zürich tkjang@iis.ee.ethz.ch Abbas Rahimi UC Berkeley abbas@eecs.berkeley.edu Simone Benatti Università di Bologna simone.benatti@unibo.it Corresponding Topical Editor Roman Lysecky University of Arizona, Tucson rlysecky@ece.arizona.edu
Last updated by Dou Sun in 2020-05-07
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