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VDAT 2026: International Symposium on VLSI Design and Test

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VDAT
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截稿日期:
2026-04-30
通知日期:
2026-06-30
会议日期:
2026-08-20
会议地点:
Noida, Uttar Pradesh, India
届数:
30
浏览: 1220   关注: 0   参加: 0

会伴指数 (CP-I)

52.6 / 100
全站第 1,126 名 / 共 5,693 个会议 · 前 20%

系统与体系结构 第 133 / 341

学术认可 (35%) 无数据 —— 按中性基准 50 分计入 —
投稿选择性 (20%) 无数据 —— 按中性基准 50 分计入 —
会议传承 (20%)
92
社区关注 (10%)
13
资料公开度 (15%)
35

用到的输入: 有据可查的届次：30 · 过去 24 个月打开过本页的研究者：5 人

公开资料里还缺: 历年录用率 (+4.5) · 历届信息 (+3.0) · 最佳论文记录 (+2.3)
主办方认领本会议后，可直接在这一页补上；分数每晚重算。如何提升这个分数

置信度 45% —— 分数中有多大比例来自实际观测到的数据，而不是中性基准。 这个分数是怎么算出来的 · 查看完整榜单 · 算法版本 1.1 · 算于 2026-10-04

征稿

VDAT 2026 (International Symposium on VLSI Design and Test) is an academic conference held in Noida, Uttar Pradesh, India on 2026-08-20. The paper submission deadline is 2026-04-30. Acceptance notifications are sent on 2026-06-30.

Conference Tracks Track 1 : VLSI & System-on-Chip (SoC) Design Digital, Analog & Mixed-Signal Design Low-Power & High-Performance Architectures Heterogeneous SoC Integration Embedded & Real-Time Systems Memory Subsystems & On-Chip Interconnects Track 2 : Nanoelectronics, Emerging Devices & Beyond-CMOS Technologies FinFET, GAA, Nanosheet & Advanced Transistor Structures 2D Materials & Novel Semiconductor Devices Spintronics & Neuromorphic Devices Device Modeling & Reliability Cryogenic & Advanced Device Technologies Track 3 : Electronic Design Automation (EDA), CAD & AI-Driven Design Physical Design & Place-and-Route Design Space Exploration AI/ML for EDA & Automation Statistical & Formal Verification Design Automation for Advanced Technology Nodes Track 4 : Design Automation for Advanced Technology Nodes Hardware Accelerators for Deep Learning Edge AI & Low-Power AI Systems In-Memory & Near-Memory Computing for AI AI for Semiconductor Manufacturing & Yield Efficient Architectures for LLMs & Emerging AI Models Track 5 : Verification, Testing, Reliability & Hardware Security Design-for-Testability (DFT) & Built-In Self-Test (BIST) Hardware Trust & Security Architectures Fault Tolerance & Resilient Systems Aging, Variability & Radiation Effects Secure SoC & Cryptographic Hardware Track 6 : 3D-IC, Advanced Packaging & Heterogeneous Integration 2.5D/3D IC Integration Chiplets & System-in-Package Thermal & Power Integrity in 3D Systems Advanced Interconnect & TSV Technologies Packaging Solutions for AI & High-Performance Systems Track 7 : Quantum & Future Computing Architectures Quantum Computing Devices & Architectures Quantum Circuit Design & Error Correction Cryogenic CMOS for Quantum Systems A Beyond-CMOS Computing Paradigms Hybrid Classical–Quantum Architectures
由 Dou Sun 最后更新于

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