会议信息

VTS 2027: VLSI Test Symposium

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VTS
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截稿日期:
2026-11-13 还有 55 天
通知日期:
2027-01-29
会议日期:
2027-04-26
会议地点:
Napa, California, USA
届数:
CCF: C   QUALIS: A2   浏览: 36507   关注: 21   参加: 2

会伴指数 (CP-I)

75.2 / 100
全站第 259 名 / 共 5,682 个会议 · 前 5%

系统与体系结构 第 50 / 341

学术认可 (35%)
92
投稿选择性 (20%) 无数据 —— 按中性基准 50 分计入 —
会议传承 (20%)
100
社区关注 (10%)
47
资料公开度 (15%)
55

用到的输入: 收录等级：CCF C, QUALIS A2 · 有据可查的届次：45 · 在会伴关注它的研究者：21 人 · 过去 24 个月打开过本页的研究者：9 人

公开资料里还缺: 历年录用率 (+4.5) · 最佳论文记录 (+2.3)
主办方认领本会议后，可直接在这一页补上；分数每晚重算。如何提升这个分数

置信度 80% —— 分数中有多大比例来自实际观测到的数据，而不是中性基准。 这个分数是怎么算出来的 · 查看完整榜单 · 算法版本 1.1 · 算于 2026-09-19

征稿

VTS 2027 (VLSI Test Symposium) is a CCF C / QUALIS A2 conference held in Napa, California, USA on 2027-04-26. The paper submission deadline is 2026-11-13. Acceptance notifications are sent on 2027-01-29.

You are invited to participate and submit your contributions to VTS’27. The areas of interest include (but are not limited to) the following topics: VTS Topics Generative AI Applications in Test and Security Silicon Lifecycle Management Silent Data Corruption Test-Enabled Digital Twin Analog – Mixed-Signal – RF Test ATPG and Compression Automotive Test and Safety Built-In Self-Test (BIST) Functional safety Digital twin-enabled test and security High BW Test through High-Speed Interfaces Testing for extreme environments Test og Non-Si and Compound Circuits Test and Security of Quantum Circuits Test and Security of Photonic Circuits Test and Security of Emerging Memory Technologies Functional Debug through Scan Fault Modeling and Simulation Low-Power IC Test Machine Learning for Test and Security Microsystems/MEMS/Sensors Test Memory Test and Repair Test for 3D and Heterogenous Integration Yield Optimization Online Test and Error Correction Power and Thermal Issues in Test System-on-Chip (SOC) Test Test and Reliability of Biomedical Devices Test and Reliability of High-Speed I/O Test and Security of Machine Learning Hardware Test Standards FPGA Test Defect-Based Test Defect and Fault Tolerance Delay and Performance Test Design for Testability Post-silicon Validation and Debug Hardware Security Embedded System and Board Test
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