Conference Information

VTS 2027: VLSI Test Symposium

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Submission Date:
2026-11-13 Due in 55 days
Notification Date:
2027-01-29
Conference Date:
2027-04-26
Location:
Napa, California, USA
Years:
CCF: C   QUALIS: A2   Viewed: 36508   Tracked: 21   Attend: 2

Conference Partner Index (CP-I)

75.2 / 100
Ranked #259 of 5,682 conferences · Top 5%

#50 of 341 in Systems & Architecture

Academic recognition (35%)
92
Submission selectivity (20%) No data - scored at the neutral baseline of 50 —
Editions held (20%)
100
Community attention (10%)
47
Public record completeness (15%)
55

Inputs used: Listed as CCF C, QUALIS A2 · Editions on record: 45 · Researchers following it here: 21 · Researchers who opened this page in the past 24 months: 9

Missing from the public record: Historical acceptance rates (+4.5) · Best-paper records (+2.3)
Organizers can add these from this page after claiming the conference; scores are recomputed nightly. How to raise this score

Confidence 80% - the share of the score backed by observed data rather than the neutral baseline. How this score is calculated · Browse the ranking · Algorithm version 1.1 · Computed 2026-09-19

Call For Papers

VTS 2027 (VLSI Test Symposium) is a CCF C / QUALIS A2 conference held in Napa, California, USA on 2027-04-26. The paper submission deadline is 2026-11-13. Acceptance notifications are sent on 2027-01-29.

You are invited to participate and submit your contributions to VTS’27. The areas of interest include (but are not limited to) the following topics: VTS Topics Generative AI Applications in Test and Security Silicon Lifecycle Management Silent Data Corruption Test-Enabled Digital Twin Analog – Mixed-Signal – RF Test ATPG and Compression Automotive Test and Safety Built-In Self-Test (BIST) Functional safety Digital twin-enabled test and security High BW Test through High-Speed Interfaces Testing for extreme environments Test og Non-Si and Compound Circuits Test and Security of Quantum Circuits Test and Security of Photonic Circuits Test and Security of Emerging Memory Technologies Functional Debug through Scan Fault Modeling and Simulation Low-Power IC Test Machine Learning for Test and Security Microsystems/MEMS/Sensors Test Memory Test and Repair Test for 3D and Heterogenous Integration Yield Optimization Online Test and Error Correction Power and Thermal Issues in Test System-on-Chip (SOC) Test Test and Reliability of Biomedical Devices Test and Reliability of High-Speed I/O Test and Security of Machine Learning Hardware Test Standards FPGA Test Defect-Based Test Defect and Fault Tolerance Delay and Performance Test Design for Testability Post-silicon Validation and Debug Hardware Security Embedded System and Board Test
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