Conference Information

DATE 2027: Design, Automation and Test in Europe

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Submission Date:
2026-09-07
Notification Date:
2026-11-10
Conference Date:
2027-03-22
Location:
Dresden, Germany
Years:
CCF: B   ICORE: A   QUALIS: A1   Viewed: 967804   Tracked: 154   Attend: 25

Conference Partner Index (CP-I)

92.8 / 100
Ranked #29 of 5,680 conferences · Top 1%

#1 of 469 in Robotics & Control

Academic recognition (35%)
100
Submission selectivity (20%)
82
Editions held (20%)
92
Community attention (10%)
79
Public record completeness (15%)
100

Inputs used: Listed as CCF B, ICORE A, QUALIS A1 · Acceptance rate: 26.7% (mean of 2 editions on file) · Editions on record: 30 · Researchers following it here: 154 · Researchers who opened this page in the past 24 months: 55

Confidence 100% - the share of the score backed by observed data rather than the neutral baseline. How this score is calculated · Browse the ranking · Algorithm version 1.1 · Computed 2026-09-11

Call For Papers

DATE 2027 (Design, Automation and Test in Europe) is a CCF B / ICORE A / QUALIS A1 conference held in Dresden, Germany on 2027-03-22. The paper submission deadline is 2026-09-07. Acceptance notifications are sent on 2026-11-10.

Areas of Interest Within the scope of the conference, the main areas of interest are: design automation, design tools and hardware architectures for electronic and embedded systems; test and dependability at system, chip, circuit and device level for analogue and digital electronics; modelling, analysis, design and deployment of embedded software and cyber-physical systems; application design and industrial design experiences. Topics of interest include, but are not restricted to: • System-level design methodologies and high-level synthesis • System simulation and validation • Formal methods and verification • Design and test for analogue and mixed-signal circuits and systems, and MEMS • Design and test of hardware security primitives • Design and test of secure systems • Network on chip and on-chip communication • Architectural and microarchitectural design • Low-power, energy-efficient and thermal-aware design • Approximate computing • Reconfigurable systems • Logical analysis and design • Physical analysis and design • Emerging design technologies for future computing • Emerging design technologies for future memories • Design Automation for Quantum Computing • Power-efficiency and Smart Energy Systems for Sustainable Computing • Smart Society and Digital Wellness • Secure Systems, Circuits and Architectures • Autonomous Systems and Smart Industry • Applications of Artificial Intelligence Systems • Applications of Emerging Technologies • Modelling and mitigation of defects, faults, variability, and reliability • Test generation, test architectures, design for test, and diagnosis • Dependability and system-level test • Embedded software architecture, compilers and tool chains • Real-time, dependable and privacy-enhanced systems • Machine learning solutions for embedded and cyberphysical systems • Design methodologies for machine learning architectures • Design modelling and verification for embedded and cyber-physical systems
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Acceptance Ratio

Average acceptance rate: 26.7% over 2 years (2005–2006).

YearSubmittedAcceptedAccepted(%)
200683426732%
200582517621.3%

Best Papers

YearBest Papers
2026FSDB: A Folded-Store Dynamic-Broaden Hybrid Compute-in-ROM/SRAM Architecture for Deploying Large-Scale DNNs On-Chip
2026KirbyMM: Outer-Product Based Matrix Multiplication on ARMv9 Processor
2026RIFT: A Scalable Methodology for LLM Accelerator Fault Assessment using Reinforcement Learning
2026Torrent: A distributed DMA for Efficient and Flexible Point-to-Multipoint Data Movement
2026INSPIRE: In-Sensor Compressed Weight Retrieval for Enhancing ViTEfficiency at Edge
2025Timing Driven Global Placement by Efficient Critical Path Extraction
2025A Lightweight CNN for Real Time Pre Impact Fall Detection
2025A Soft Error Tolerant Flip Flop for eFPGA Configuration Hardening in 22nm FinFET Process
2025Cocktail: Chunk Adaptive Mixed Precision Quantization for Long Context LLM Inference
2024FusionArch: A Fusion-Based Accelerator for Point-Based Point Cloud Neural Networks
2024HW-SW Optimization of DNNs for Privacy-preserving People Counting on Low-resolution Infrared Arrays
2024SELCC: Enhancing MLC Reliability and Endurance with Single-Cell Error Correction Codes
2024Efficient Exploration of Cyber-Physical System Architectures Using Contracts and Subgraph Isomorphism
2023Hardware Efficient Weight-Binarized Spiking Neural Networks
2023Automated Energy-Efficient DNN Compression under Fine-Grained Accuracy Constraints
2023SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility
2023PRADA: Point Cloud Recognition Acceleration via Dynamic Approximation
2022FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler
2022Algorithm-Hardware Co-Design for Efficient Brain-Inspired Hyperdimensional Learning on Edge
2022Self-Terminated Write of Multi-Level Cell ReRAM for Efficient Neuromorphic Computing
2022Efficient Global Robustness Certification of Neural Networks via Interleaving Twin-Network Encoding
2021Adaptive Design of Real-Time Control Systems subject to Sporadic Overruns
2021Leveraging Processor Modeling and Verification for General Hardware Modules
2021A GPU-accelerated Deep Stereo-LiDAR Fusion for Real-time High-precision Dense Depth Sensing
2021Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core
2020DEFCON: Generating and Detecting Failure-prone Instruction Sequences via Stochastic Search
2020Statistical Time-based Intrusion Detection in Embedded Systems
2020A Flexible and Scalable NTT Hardware: Applications from Homomorphically Encrypted Deep Learning to Post-Quantum Cryptography
2020Impact of Magnetic Coupling and Density on STT-MRAM Performance
2019Enhancing Reliability of STT-MRAM Caches by Eliminating Read Disturbance Accumulation
2019When Capacitors Attack: Formal Method Driven Design and Detection of Charge-Domain Trojans
2019Error-Shielded Register Renaming Subsystem for a Dynamically Scheduled Out-of-Order Core
2019Data Subsetting: A Data-Centric Approach to Approximate Computing
2018Buffer-aware bounds to multi-point progressive blocking in priority-preemptive NoCs
2018Low-Cost High-Accuracy Variation Characterization for Nanoscale IC Technologies via Novel Learning-based Techniques
2018MATIC: Learning Around Errors for Efficient Low-Voltage Neural Network Accelerators
2018Efficient Verification Of Multi-Property Designs (The Benefit Of Wrong Assumptions)
2017CoSyn: Efficient Single-Cell Analysis Using a Hybrid Microfluidic Platform
2017Automatic Place-and-Route of Emerging LED-Driven Wires within a Monolithically-Integrated CMOS+III-V Process
2017Fast and Waveform-Accurate Hazard-Aware SAT-Based TSOF ATPG
2017MoDNN: Local Distributed Mobile Computing System for Deep Neural Network
2016UTILIZING MACROMODELS IN FLOATING RANDOM WALK BASED CAPACITANCE
2016OTEM: OPTIMIZED THERMAL AND ENERGY MANAGEMENT FOR HYBRID ELECTRICAL ENERGY STORAGE IN ELECTRIC VEHICLES
2016MODELING FABRICATION NON-UNIFORMITY IN CHIP-SCALE SILICON PHOTONIC INTERCONNECTS
2016PROBABILISTIC WCET ESTIMATION IN PRESENCE OF HARDWARE FOR MITIGATING THE IMPACT OF PERMANENT FAULTS
2015PHASE-NOC: TDM SCHEDULING AT THE VIRTUAL-CHANNEL LEVEL FOR EFFICIENT NETWORK TRAFFIC ISOLATION
2015HARDWARE TROJAN DETECTION FOR GATE-LEVEL ICS USING SIGNAL CORRELATION BASED CLUSTERING
2015DIGITAL CIRCUITS RELIABILITY WITH IN-SITU MONITORS IN 28NM FULLY DEPLETED SOI
2009Analysis and optimization of NBTI induced clock skew in gated clock trees
2009Gate sizing for large cell-based designs
2009On linewidth-based yield analysis for nanometer lithography
2008Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set
2008Retargetable Code Optimization for Predicated Execution
2008Analysis and Optimization of the Recessed Probe Launch for High Frequency Measurements of PCB Interconnects
2008Power Balanced Gates Insensitive to Routing Capacitance Mismatch
2007Statistical blockade: a novel method for very fast Monte Carlo simulation of rare circuit events, and its application
2007Compositional specification of behavioral semantics
2006A dynamically reconfigurable packet-switched network-on-chip
2006Optimizing sequential cycles through Shannon decomposition and retiming
2006An effective technique for minimizing the cost of processor software-based diagnosis in SoCs
2005Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices
2005Design Optimization of Time-and Cost-Constrained Fault-Tolerant Distributed Embedded Systems
2005Systematic Transaction Level Modeling of Embedded Systems with SystemC
2005An Application-Specific Design Methodology for STbus Crossbar Generation
2004Poor Mans TBR: A Simple Model Reduction Scheme
2004Wrapper Design for Testing IP Cores with Multiple Clock Domains
2004Digital Ground Bounce Reduction by Phase Modulation of the Clock
2004Automatic Synthesis and Simulation of Continuous-Time [Sigma-Delta] Modulators
2003Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step
2003Validating SAT Solvers Using an Independent Resolution-Based Checker: Practical Implementations and Other Applications
2003Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
2002Using Problem Symmetry in Search Based Satisfiability Algorithms
2002Analysis of Nonlinearities in RF Front-End Architectures Using a Modified Volterra Series Approach
2002Reducing Test Application Time Through Test Data Mutation Encoding
2001Probabilistic application modeling for system-level perfromance analysis
2001SystemCSV - an extension of SystemC for mixed multi-level communication modeling and interface-based system design
2001Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding
2000Techniques for Reducing Read Latency of Core Bus Wrappers
2000Code Selection for Media Processors with SIMD Instructions
2000Cost Reduction and Evaluation of a Temporary Faults Detecting Technique
1999A CAD Framework for Generating Self-Checking 1 Multipliers Based on Residue Codes
1999Symbolic Functional Vector Generation for VHDL Specifications
1998Reduced-Order Modeling of Large Linear Passive Multi-Terminal Circuits Using Matrix-Pade Approximation
1998Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays

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