Conference Information

ITC 2026: International Test Conference

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Submission Date:
2026-03-20
Notification Date:
2026-06-19
Conference Date:
2026-10-11
Location:
San Antonio, Texas, USA
CCF: b   CORE: b   QUALIS: a1   Viewed: 155197   Tracked: 24   Attend: 0

Call For Papers

ITC 2026 (International Test Conference) is a CCF B / CORE B / QUALIS A1 conference held in San Antonio, Texas, USA on 2026-10-11. The paper submission deadline is 2026-03-20. Acceptance notifications are sent on 2026-06-19.

ITC invites submissions on the latest advances in test, validation, diagnosis, implementation, and scalability for ICs, boards, and systems, covering cross-domain, test economics, and product lifecycle challenges. Topics of interest include, but not limited to Test Methodologies & Technologies • Adaptive Test in Practice • ATE & Probe Card Design • Built-In Self-Test (BIST) • Boundary Scan & JTAG • Design for Test (DFT) & DFM • Mixed-Signal & Analog Test • Memory Test & Repair • MEMS Testing • Power Issues in Test • High-Speed I/O, RF & Jitter Test • Test Compression & Optimization • Test Generation & Validation Industrial Case Study, System, & Application Specific Test • 3D/2.5D & Advanced Packaging • SoC/NoC Test • 5G/6G Test • Hardware Security & Trust • Automotive Test • IoT Test • System Test • Silicon case studies Verification, Debug & Analysis • Pre-Silicon/Post-Silicon Verification • Silicon Debug & Field Monitoring • Diagnosis & Defect Analysis • Data-Driven Test & End-to-End Analytics • Yield Analysis & Optimization • Test-to-Design Feedback & Escape Analysis Emerging Topics • Reliability & Resilience • Emerging Defect Mechanisms • Protocol-Aware Test • Optics & Photonics Test • AI/Machine Learning in Test • Quantum Device Testing • KGD/KGS/KGP Economics • New Technologies & Standards
Last updated by Dou Sun in

Acceptance Ratio

Average acceptance rate: 22.3% over 6 years (2012–2025).

YearSubmittedAcceptedAccepted(%)
20251644024.4%
20241553623.2%
20231623018.5%
20142506224.8%
20132504618.4%
20122506124.4%

Best Papers

YearBest Papers
2024WM-Graph: Graph-Based Approach for Wafermap Analytics
2024Generation and Quality Evaluation of Synthetic Process Control Monitoring Data
2024Digital Scan and ATPG for Analog Circuits
2023IEA-Plot: Conducting Wafer-Based Data Analytics Through Chat
2023ARC-FSM-G: Automatic Security Rule Checking for Finite State Machine at the Netlist Abstraction
2022Language Driven Analytics for Failure Pattern Feedforward and Feedback
2022PPA Optimization of Test Points in Automotive Designs
2022DEFCON: Defect Acceleration through Content Optimization
2021Exploiting Application Tolerance for Functional Safety
2021Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization
2021A Fast and Low Cost Embedded Test Solution for CMOS Image Sensors
2020Learning A Wafer Feature With One Training Sample
2020Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs
2020Industrial Application of IJTAG Standards to the Test of Big-A/little-d devices
2019Efficient Analog Defect Simulation
2019Deploying a Machine Learning Solution as a Surrogate
2018Concept Recognition in Production Yield Data Analytics
2018Fast and accurate linearity test for DACs with various architectures using segmented models
2017A Single-Pin Test Control for Low-Pin-Count Big A, little d Devices
2017Safety Analysis for Integrated Circuits in the Context of Hybrid Systems
2016Power Supply Impedance Emulation to Eliminate Overkills and Underkills Due to the Impedance Difference Between ATE and Customer Board
2015A Structured Approach to Post Silicon Validation and Debug using Symbolic Quick Error Detect
2014Yield Optimization Using Advanced Statistical Correlation Methods
2013Test Time Reduction with SATOM: Simultaneous AC-DC Test with Orthogonal Multi-excitations
2012Algorithm for Dramatically Improved Efficiency in ADC Linearity Test
2011Real-Time Testing Method for 16 Gbps 4-PAM Signal Interface
2010Lessons from At-Speed Scan Deployment on an Intel Itanium Microprocessor
2010Adaptive Test Flow for Mixed-Signal RF Circuits Using Learned Information from Device Under Test
2009Voltage Transient Detection and Induction for Debug and Test
2009A Robust Method for Identifying a Deterministic Jitter Model in a Total Jitter Distribution
2008Efficiently Performing Yield Enhancements by Identifying Dominant Physical Root Cause from Test Fail Data
2008A Method to Generate a Very-Low-Distortion, High-Frequency Sine Waveform Using an AWG
2008Test Access Mechanism for Multiple Identical Cores
2007On-Chip Timing Uncertainty Measurements on IBM Processors
2006Signature Based Diagnosis for Logic BIST
2005Structural Tests for Jitter Tolerance in SerDes Receivers
2004A New Probing Technique for High-Speed/High-Density Printed Circuit Boards
2004In Search of the Optimum Test Set-Adaptive Test Methods for Maximum Defect Coverage and Lowest Test Cost
2004Random and Systematic Defect Analysis Using IDDQ Signature Analysis for Understanding Fails and Guiding Test Decisions
2003Elimination of Traditional Functional Testing of Interface Timings at Intel
2003Convolutional Compaction of Test Responses
2002Complete, Contactless I/O Testing – Reaching the Boundary in Minimizing Digital IC Testing Cost
2002Architecting Millisecond Test Solutions for Wireless Phone RFICs
2001Neighbor Selection for Variance Reduction in IDDQ and Other Parametric Data
2001Debug Methodology for the McKinley Processor
2000A Stand-alone Integrated Test Core for Time and Frequency Domain Measurements
2000Logic Mapping on a Microprocessor
1999Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
1999Logic BIST for Large Industrial Designs: Real Issues and Case Studies
1999BIST for Phase-Locked Loops in Digital Applications
1999The Attack of the ‘Holey Shmoos’: A Case Study of Advanced DFD and Picosecond Imaging Circuit Analysis (PICA)
1998Defect Detection with Transient Current Testing and its Potential for Deep Sub-micron CMOS ICs
1998Failure Analysis of Timing and IDDQ-only Failures from the SEMATECH Test Methods Experiment
1998Probabilistic Mixed-Model Fault Diagnosis
1997Current Signatures: Application
1997Intrinsic Leakage in Low-Power Deep-Submicron CMOS ICs
1996Weak-Write Test Mode: an SRAM Cell Stability Design for Test Technique
1996Early Capture for Boundary Scan Timing Measurments
1996Process-Aggravated Noise: New Validation and Test Problem
1995Improved Boundary Scan Design
1995Improving DSP-Based Measurements with Spectral Interpolation
1994Defect Classes – An Overdue Paradigm for CMOS IC Testing
1994An Analog Multi-Tone Signal Generator for Built-In Self Test
1993Structure and Metrology for an Analog Testability Bus
1993A BIST Scheme for an SNR Test of a Sigma-Delta ADC
1992A Comparison of Defect Models for Fault Location with IDDQ Measurements
1992High-Performance Pin Electronics with GaAs, A Contradiction in Terms?
1992A Proposed Method of Accessing 1149.1 in a Backplane Environment
1991The Effect of Different Test Sets on Quality Level Prediction: When is 80% Better Than 90%?
1991Implementing 1149.1 on CMOS Microprocessors
1990CMOS Bridge Fault Detection
1990Frequency Enhancement of Digital Test Systems
1990Increased CMOS Stuck-at Fault Coverage with Reduced IDDQ Test Sets
1989Built-in Self-Test of the Macrolan Chip
1989A High-Performance, 10-Volt Integrated Pin Electronics Driver
1989A 250-MHz Shared-Resource VLSI Test System with High Pin-Count and Memory Test Capability
1988Membrane Probe Card Technology – The Future for High-Performance Wafer Test
1988Test Head Design Using Electro-Optic Receivers and GaAs Pin Electronics for a Gigahertz Production Test System
1988Statistical Delay Fault Coverage and Defect Level for Delay Faults
1987Hierarchical Test Generation: Can AI Help?
1987A Generic Procedure for Evaluating VLSI Test System Timing Accuracy
1986Reliability and IC Electrical Properties of Gate Oxide Shorts
1986Comparison of Aliasing Errors for Primitive and Non-Primitive Polynomials
1986ISDN Device Testing Demands A New Level of Performance from Automatic Test Equipment
1985The Electrical Behavior of Gate-Oxide Short Defects
1984Random Testing for Stuck-at-Storage Cells in an Embedded Memory
1983New Techniques for High-Speed Analog Testing
1983HITEST – Intelligent Test Generation
1983Subnanosecond Timing Measurements on MOS Devices Using Modern VLSI Test Systems
1982Testability Measures – What do they tell us?
1981Automated Measurement of 12- to 16-bit Converters
1980Electron Beam Testing of Microprocessors
1980Testing for Bipolar Integrated Circuit Failures
1980A New Approach to High-Speed Codec Testing
1980Soft Error Testing
1979Design for Self-Verification: An Approach for Dealing with Testability Problems in VLSI-Based Designs

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