Conference Information

ICCAD 2026: International Conference on Computer-Aided Design

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Submission Date:
2026-04-07
Notification Date:
2026-07-11
Conference Date:
2026-11-08
Location:
San Jose, California, USA
Years:
45
CCF: B   ICORE: A   QUALIS: A1   Viewed: 200709   Tracked: 103   Attend: 10

Conference Partner Index (CP-I)

90.5 / 100
Ranked #57 of 5,646 conferences · Top 1%

#16 of 341 in Systems & Architecture

Academic recognition (35%)
100
Submission selectivity (20%)
83
Editions held (20%)
100
Community attention (10%)
70
Public record completeness (15%)
80

Inputs used: Listed as CCF B, ICORE A, QUALIS A1 · Acceptance rate: 26.3% (mean of 1 editions on file) · Editions on record: 45 · Researchers following it here: 103 · Researchers who opened this page in the past 24 months: 26

Missing from the public record: Past editions (+3.0)
Organizers can add these from this page after claiming the conference; scores are recomputed nightly. How to raise this score

Confidence 100% - the share of the score backed by observed data rather than the neutral baseline. How this score is calculated · Browse the ranking · Algorithm version 1.1 · Computed 2026-08-30

Call For Papers

ICCAD 2026 (International Conference on Computer-Aided Design) is a CCF B / ICORE A / QUALIS A1 conference held in San Jose, California, USA on 2026-11-08. The paper submission deadline is 2026-04-07. Acceptance notifications are sent on 2026-07-11.

Jointly sponsored by IEEE and ACM, IEEE/ACM ICCAD is the premier forum to explore new challenges, present leading-edge innovative solutions, and identify emerging technologies in the electronic design automation research areas. IEEE/ACM ICCAD covers the full range of CAD topics – from device and circuit level up through system level, as well as post-CMOS design. IEEE/ACM ICCAD has a long-standing tradition of producing cutting-edge, innovative technical program for attendees. Covered Topics Original technical submissions on, but not limited to, the following topics are invited: System Modeling: HW/SW co-design, simulation, & heterogeneous SoCs. AI & Accelerators: Neural network hardware, AI algorithms, & CAD for AI. Embedded Systems & Edge Computing: Cyber-physical systems, FPGAs, & CGRAs. Security: Hardware trust, encryption, & side-channel attack prevention. Efficiency: Low-power & approximate computing. Logic Synthesis: Technology mapping & optimization. Physical Design: Floorplanning, placement, routing, & CTS. Verification & Test: Formal verification, emulation, ATPG, & post-silicon debug. Analysis: Timing, power, and signal integrity optimization. Manufacturability: DFM, yield estimation, & reliability analysis. Analog/Mixed-Signal: RF device modeling & EM simulation. Nanoscale & Post-CMOS: Emerging devices, nanophotonics, & CAD for mixed-domain & field-coupled technologies. Advanced Computing Paradigms: Non-von Neumann architectures, quantum computing, DNA computing, neuromorphic hardware, swarm intelligence & green computing. Bio-CAD: CAD for microfluidics, bio-sensors, & synthetic biology More details on the covered topics and the submission process will be shared on the ICCAD website.
Last updated by Dou Sun on

Acceptance Ratio

Average acceptance rate: 26.3% over 1 years (2003–2003).

YearSubmittedAcceptedAccepted(%)
200349012926.3%

Best Papers

YearBest Papers
2019Analyzing and Modeling In-Storage Computing Workloads On EISC — An FPGA-Based System-Level Emulation Platform
2019Power Grid Fixing for Electromigration-Induced Voltage Failures
2018DNNBuilder: An Automated Tool for Building High-performance DNN Hardware Accelerators for FPGAs
2018PolyCleaner: Clean Your Polynomials Before Backward Rewriting to Verify Million-gate Multipliers
2017COMBA: A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications
2017SALT: Provably Good Routing Topology by a Novel Steiner Shallow-Light Tree Algorithm
2016Fast Physics-Based Electromigration Checking for On-Die Power Grids
2016Malicious LUT: A Stealthy FPGA Trojan Injected and Triggered by the Design Flow
2015Defect Clustering-Aware Spare-TSV Allocation for 3D ICs
2015A Polyhedral-based SystemC Modeling and Generation Framework for Effective Low-power Design Space Exploration
2014Modeling and Analysis of Nonstationary Low-Frequency Noise in Circuit Simulators: Enabling Non Monte Carlo Techniques
2014Using Multi-Level Cell STT-RAM for Fast and Energy-Efficient Local Checkpointing
2013Improved SAT-based ATPG: More Constraints, Better Compaction
2013Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography
2012Stability Assurance and Design Optimization of Large Power Delivery Networks with Multiple On-Chip Voltage Regulators
2011Formal Verification of Phase- Locked Loops Using Reachability Analysis and Continuization
2011Gate Sizing and Device Technology Selection Algorithms for High-Performance Industrial Designs
2010SimPL: An effective placement algorithm
2009TAPE: Thermal-aware agent-based power econom multi/many-core architectures
2008Guaranteed stable projection-based model reduction for indefinite and unstable linear systems
2007Approximation algorithm for the temperature-aware scheduling problem
2006Joint Design-Time and Post-Silicon Minimization of Parametric Yield Loss using Adjustable Robust Optimization
2005FastSies: a fast stochastic integral equation solver for modeling the rough surface effect
2004SPRIM: structure-preserving reduced-order interconnect macromodeling
2004Asymptotic probability extraction for non-normal distributions of circuit performance
2003Block-based Static Timing Analysis with Uncertainty
2002A Local Circuit Topology for Inductance Parasitics
2002Metrics for Structural Logic Synthesis
1991The Effects of False Paths in High-Level Synthesis
1991Exact Zero Skew

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