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DAC 2026: Design Automation Conference

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Día de Entrega:
2025-11-11
Fecha de Notificación:
2026-03-09
Fecha de conferencia:
2026-07-26
Ubicación:
Long Beach, California, USA
Ediciones:
63
ICORE: A*   QUALIS: A1   Vistas: 960295   Seguidores: 125   Asistentes: 22

Solicitud de Artículos

DAC 2026 (Design Automation Conference) is a ICORE A* / QUALIS A1 conference held in Long Beach, California, USA on 2026-07-26. The paper submission deadline is 2025-11-11. Acceptance notifications are sent on 2026-03-09.

DAC is the premier conference for the design and automation of electronic circuits and systems. Research papers, technical presentations and sessions are selected by a committee of electronic design experts that offer the latest information on recent developments, trends, management practices, new products, technologies and methodologies. Submit to DAC 2026 and be part of tomorrow’s innovation. Topics of Interest AI The Artificial Intelligence (AI) program highlights the advances in the field with a focus on leading AI designs and AI usage in design automation. While artificial intelligence and neural network research has been ongoing for more than half a century, recent advances in computing and acceleration of the pace and scale of machine learning (ML) are revolutionizing the impact of artificial intelligence on every aspect of our daily lives, ranging from smart consumer electronics and services to self-navigating cars and personalized medicine. While AI was already changing computing from devices through near and far edges all the way to datacenters, more recently, the advances in Generative AI are further transforming our day to day lives and the way electronics is developed from chips to systems. The AI sessions at DAC focuses on the fundamentals, accomplishments to date, and challenges ahead in development of ML/AI hardware, software and systems as well as application of AI/ML in design automation, providing a forum for researchers and practitioners across all the widely varying disciplines involved to connect, engage, and join in shaping the future of this exciting field. Design DAC has served as a meeting place for designers of electronics from chips to systems for over five decades. Increasingly, the challenges faced by the industry require co-optimization of design, methodologies and tools that can only be achieved using cross-domain interaction of researchers and practitioners. DAC serves this need by covering design as a topic area in the research and engineering tracks. The design topics covered in the research track include the design of cyber-physical, System-on-Chip (SoC) and multi-die architectures, accelerator-based computing, emerging models of computation such as brain-inspired and quantum computing, digital and analog circuits, and emerging device technologies. Separately the Engineering Track allows tool users to share challenges and benefits of different tools, flows, and methodologies for IP, front-end, back-end as well as systems and software design, and provides excellent opportunities for education and networking between end users and tool developers. There is no other way to improve your “design IQ” in such a short amount of time than to attend the Engineering Track EDA Electronic Design Automation (EDA) is even more important now with the continuous scaling of semiconductor devices, blending development requirements from chips to systems and extending beyond electronics into interactions with mechanical, electromagnetic effects of system design. Demands for lower power, higher reliability, and more agile electronic systems raise new challenges to design automation enabling such systems. For the past five decades, the primary focus of the research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems. In addition to the traditional EDA topics ranging from physical design to system architectures, DAC features high-quality papers on design research, design practices, and design automation for cross-cutting topics including low-power, reliability, multicore/application-specific/heterogeneous architectures, 3-D integrations, multi-die systems, emerging device technologies, design automation of "things", and their applications. DAC's EDA technical program has ensured the best-in-class solutions that promise to advance EDA. Security Security sessions at DAC address an urgent need to create, analyze, evaluate, and improve the hardware, embedded systems and software base of the contemporary security solutions. Secure and trustworthy software and hardware components, platforms and supply chains are vital to all domains including financial, healthcare, transportation, and energy. Security of systems is becoming equally important. A revolution is underway in many industries that are "connecting the unconnected". Cyber physical systems, e.g., automobiles, smart grid, medical devices, etc., are taking advantage of integration of physical systems with the information systems. Not withstanding the numerous benefits, these systems are appealing targets of attacks. Attacks on the cyber-part of such systems can have disastrous consequences in the physical world. The scope and variety of attacks on these systems present design challenges that span embedded hardware, software, networking, and system design. Security topics will be featured through invited special sessions, panels, and lecture/poster presentations by both practitioners and researchers to share their knowledge and experience on this evolving environment. Systems Systems Design is the art of choosing and designing the proper combination of hardware and software components to achieve system-level design goals like speed, efficiency, reliability, security, and safety. Systems Design is an increasingly diverse, disruptive, and challenging field for designs ranging from data centers, mobile devices, medical devices, automotive, consumer, robotics, drones, industrial applications and beyond. Software at the embedded scale is built into devices that may not necessarily be recognized as computing devices (e.g., thermostats, toys, defibrillators, and anti-lock brakes), but nevertheless controls the functionality and perceived quality of these devices. Software at the system-level increasingly drives system design requirements as well as workloads that determine chip and system architectures and testing. The Systems sessions at DAC provide a forum for discussing the challenges of embedded design and an opportunity for leaders in the industry and academia to come together to exchange ideas and roadmaps for the future for this rapidly expanding area.
Última actualización por Dou Sun el

Tasa de aceptación

Tasa de aceptación media: 26.1% en 10 años (2000–2014).

AñoEnviadosAceptadosAceptados(%)
201478717422.1%
201374015621.1%
201274116422.1%
200686520924.2%
200573515421%
200478516320.8%
200362815224.2%
200249114729.9%
200141016039%
200039014236.4%

Los Mejores Artículos

AñoLos Mejores Artículos
2022Towards a formally verified hardware root-of-trust for data-oblivious computing
2019Dreamplace: Deep Learning Toolkit-enabled GPU Acceleration for Modern VLSI Placement
2018Compensated-DNN: Energy Efficient Low-Precision Deep Neural Networks by Compensating Quantization Errors
2018Exact Algorithms for Delay-Bounded Steiner Arborescences
2017Toward Optimal Legalization for Mixed-Cell-Height Circuit Designs
2017Low-Power On-Chip Network Providing Guaranteed Services for Snoopy Coherent and Artificial Neural Network Systems
2016Accurate Phase-level Cross-platform Power and Performance Estimation
2016Distributed On-chip Regulation: Theoretical Stability Foundation, Over-design Reduction and Performance Optimization
2015Battery Lifetime-Aware Automotive Climate Control for Electric Vehicles
2015HAFIX: Hardware-Assisted Flow Integrity Extension
2014Containing Timing-Related Certification Cost in Automotive Systems Deploying Complex Hardware
2014Code Coverage of Assertions Using RTL Source Code Analysis
2012Triple Patterning Aware Routing and its Comparison with Double Patterning Aware Routing in 14nm Technology
2010Bayesian virtual probe: minimizing variation characterization cost for nanoscale IC technologies via Bayesian inference
2009A robust and efficient harmonic balance (HB) using direct solution of HB Jacobian
2008IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors
2008WavePipe: parallel transient simulation of analog and digital circuits on multi-core shared-memory machines
2007Period Optimization for Hard Real-time Distributed Automotive Systems
2007Interdependent Latch Setup/Hold Time Characterization via Euler-Newton Curve Tracing on State-Transition Equations
2006SAT sweeping with local observability don't-cares
2006Power grid physics and implications for CAD
2005A new canonical form for fast boolean matching in logic synthesis and verification
2005An efficient algorithm for statistical minimization of total power under timing yield constraints
2004A recursive paradigm to solve Boolean relations
2004First-order incremental block-based statistical timing analysis
2003Automatic application-specific instruction-set extensions under microarchitectural constraints
2003Random walks in a supply network
2003NORM: compact model order reduction of weakly nonlinear systems
2003The synthesis of cyclic combinational circuits
2002A universal technique for fast and flexible instruction-set architecture simulation
2002Remembrance of circuits past: macromodeling by data mining in large analog design spaces
2002Guaranteed passive balancing transformations for model order reduction
2001Energy Efficient Fixed-Priority Scheduling for Real-Time Systems on Variable Voltage Processors
2001A Practical Methodology for Early Buffer and Wire Resource Allocation
2001Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects
2001Improving Bus Test Via IDDT and Boundary Scan
2000Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips
2000A multi-interval Chebyshev collocation method for efficient high-accuracy RF circuit simulation
2000On-chip inductance modeling and analysis
2000To split or to conjoin: the question in image computation
1999Coverage Estimation for Symbolic Model Checking
1999Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design
1999Common-Case Computation: A High-Level Technique for Power and Performance Optimization
1999Improving the Test Quality for Scan-Based BIST Using a General Test Application Scheme
1999Reliability-Constrained Area Optimization of VLSI Power/Ground Networks via Sequence of Linear Programmings
1998A Decision Procedure for Bit-Vector Arithmetic
1998A Fast Hierarchical Algorithm for 3-D Capacitance Extraction
1998OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification
1998Functional Verification of a Multiple-issue, Out-of-Order, Superscalar Alpha Processor - The DEC Alpha 21264 Microprocessor
1998Generic Global Placement and Floorplanning
1997Computer-Aided Design of Free-Space Opto-Electronic Systems
1997An Improved Algorithm for Minimum-Area Retiming
1997Equivalence Checking Using Cuts and Heaps
1997Efficient Methods for Simulating Highly Nonlinear Multi-Rate Circuits
1996A Probability-Based Approach to VLSI Circuit Partitioning
1996POSE: Power Optimization and Synthesis Environment
1996HEAT: Hierarchical Energy Analysis Tool
1996Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures
1996On Solving Covering Problems
1995Verification of Arithmetic Circuits with Binary Moment Diagrams
1995DELAY: An Efficient Tool for Retiming with Realistic Delay Modeling
1995Spectral Partitioning: The More Eigenvectors, The Better
1995Behavioral Synthesis Methodology for HDL-Based Specification and Validation
1994Basic Concept of Cooperative Timing-driven Design Automation Technology for High-speed RISC Processor HARP-1
1994Resynthesis and Retiming for Optimum Partial Scan

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