ISEDA 2026 (International Symposium of EDA) is an academic conference held in Singapore on 2026-05-08. The paper submission deadline is 2026-02-28 (extended). Acceptance notifications are sent on 2026-03-25.
Original papers in, but not limited to the following areas are invited:
[1] System-Level Modeling and Design Methodology
Chairs:
Sun, Qi (Zhejiang University)
Zhao, Jieru (Shanghai Jiao Tong University)
1.1 HW/SW co-design, co-simulation and co-verification
1.2 System-level design exploration, synthesis, and optimization
1.3 System-level formal verification
1.4 System-level modeling, simulation and validation
1.5 Networks-on-chip and NoC-based system design
1.6 Constructing Hardware in Scala Embedded Language
[2] Memory Architecture and Near/In Memory Computing
Chairs:
Chen, Xiaoming (Institute of Computing Technology, CAS)
Zhang, Li (Technical University of Darmstadt)
2.1 Storage system and memory architecture
2.2 On-chip memory architectures and management: Scratchpads, compiler, controlled memories, etc.
2.3 Memory/storage hierarchies and management for emerging memory technologies
2.4 Near-memory and in-memory computing
[3] Analog-Mixed Signal Design Automation
Chairs:
Zhu, Keren (Fudan University)
Du, Li (Nanjing University)
Centurelli, Francesco (Sapienza University of Rome)
3.1 Analog/mixed-signal/RF synthesis
3.2 Analog layout, verification, and simulation techniques
3.3 High-frequency electromagnetic simulation of circuit
3.4 Mixed-signal design consideration
[4] High-Level, Behavioral, and Logic Synthesis and Optimization
Chairs:
Qian, Weikang (Shanghai Jiao Tong University)
Pilato, Christian (Politecnico di Milano)
4.1 Digital Simulation / Emulation
4.2 High-Level Synthesis
4.3 Logic Synthesis
4.4 Synthesis for Approximate Computing
[5] Analysis and Optimization for Power and Timing
Chairs:
Xie, Zhiyao (HKUST)
Li, Bing (Technische Universität Ilmenau)
5.1 Deterministic/statistical timing analysis and optimization
5.2 Process technology modeling for timing analysis
5.3 Power modeling, analysis and simulation
5.4 Low-power design and optimization at circuit and system levels
5.5 Thermal aware design and dynamic thermal management
5.6 Energy harvesting and battery management
[6] Physical Implementation
Chairs:
Ma, Yuzhe (HKUST (Guangzhou))
Lin, Yibo (Peking University)
6.1 Floorplanning, partitioning, placement and routing optimization
6.2 Interconnect planning and synthesis
6.3 Clock network synthesis
6.4 Physical design of 3D/2.5D IC and package ( e. g. , TSV, interposer, monolithic)
6.5 Post layout and post-silicon optimization
6.6 Layout Verification
[7] Testing, Validation, Simulation, and Verification
Chairs:
Zhang, Hongce (HKUST (Guangzhou))
Zheng, Yuanjin (Nanyang Technological University)
7.1 RTL and gate-leveling modeling, simulation, and verification
7.2 Circuit-level formal verification
7.3 ATPG, BIST and DFT
7.4 System test and 3D IC test, online test and fault tolerance
7.5 Memory test and repair
[8] Design for Manufacturability and Reliability
Chairs:
Chen, Yu-Guang (National Central University)
Li, Meng (Peking University)
8.1 Design-technology co-optimization (DTCO)
8.2 Standard and custom cell design and optimization
8.3 Reticle enhancement, lithography-related design optimizations and design rule checking
8.4 Design for manufacturability, yield, defect tolerance, cost issues, and DFM impact
8.5 Device-, gate, and circuit-level techniques for reliability analysis and optimization (e.g., soft error, aging, etc.)
8.6 Post-Layout optimizations
[9] Packaging & Multi-Physics Simulation
Chairs:
Peng, Yarui (Southeast University)
Tseng, Tsun-Ming (Technical University of Munich)
9.1 Extraction, TSV, and package modeling
9.2 Chiplet Design and Design tools
9.3 Chip Level Thermal Simulation
9.4 Packaging Stress Analysis
9.5 Multi-Physics Simulation
9.6 Signal/Power integrity, EM modeling and analysis
[10] Technology & Modeling
Chairs:
Ng, Kian Ann (DigiPen Institute of Technology Singapore)
Chen, Quan (Southern University of Science and Technology)
10.1 Device Compact Modeling
10.2 Process Design Kit
10.3 Semiconductor Process & Device Simulation
10.4 Cell Library Design, Characterization and Verification
10.5 New transistor/device and process technology: spintronic, phase-change, single-electron, 2D materials, etc.
[11] Emerging Technologies and Applications
Chairs:
Lee, Vincent (National University of Singapore)
Li, Xingquan (Peng Cheng Laboratory)
11.1 Biomedical, biochip, nanotechnology, MEMS
11.2 Design automation for 3D ICs and heterogeneous integration
11.3 Design automation for quantum computing
11.4 Design automation for silicon photonics
11.5 Design automation for compound semiconductors verification
[12] AI & Open Source EDA
Chairs:
Yu, Cunxi (University of Maryland)
Tan, Chee Wei (Nanyang Technological University)
12.1 Artificial Intelligence for EDA
12.2 Cloud / Parallel Computing for EDA
12.3 Open Source EDA
12.4 EDA Database
12.5 EDA Standardization
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