Conference Information

ATS 2026: Asian Test Symposium

Please Login to view website of conference
Free account: view official websites, track deadlines, and get email reminders.
Register Login
Embed deadline badge
ATS
Get this via API
Search and ranking lists need no credentials at all; full detail for this page needs a free API key. See the developer guide.
Submission Date:
2026-06-06
Notification Date:
2026-09-14
Conference Date:
2026-12-01
Location:
Kaohsiung City, Taiwan
Years:
35
CCF: C   Viewed: 34838   Tracked: 18   Attend: 1

Conference Partner Index (CP-I)

63.0 / 100
Ranked #483 of 5,658 conferences · Top 9%

#82 of 340 in Systems & Architecture

Academic recognition (35%)
66
Submission selectivity (20%) No data - scored at the neutral baseline of 50 —
Editions held (20%)
96
Community attention (10%)
53
Public record completeness (15%)
35

Inputs used: Listed as CCF C · Editions on record: 35 · Researchers following it here: 18 · Researchers who opened this page in the past 24 months: 27

Missing from the public record: Historical acceptance rates (+4.5) · Past editions (+3.0) · Best-paper records (+2.3)
Organizers can add these from this page after claiming the conference; scores are recomputed nightly. How to raise this score

Confidence 80% - the share of the score backed by observed data rather than the neutral baseline. How this score is calculated · Browse the ranking · Algorithm version 1.1 · Computed 2026-09-10

Call For Papers

ATS 2026 (Asian Test Symposium) is a CCF C conference held in Kaohsiung City, Taiwan on 2026-12-01. The paper submission deadline is 2026-06-06. Acceptance notifications are sent on 2026-09-14.

Topics — Original papers on, but not limited to, the following areas are invited: AI test and Test for AI Analog/Mixed-Signal Test ATE Design Automatic Test Pattern Generation (ATPG) Autonomous Testing Board-Level Testing and Diagnosis Boundary Scan Test Built-In Self-Test (BIST) CPU/GPU Test Connectivity Testing Defect-Based Test Delay and Performance Test Dependability and Functional Safety Design Verification, Validation, and Debug Design for Testability (DFT) Diagnosis and Silicon Debug Fault Diagnosis and Failure Analysis Fault Modeling and Simulation Fault Tolerance Hardware Oriented Security and Trust High-Speed I/O Test Heterogeneous Testing Low-Power IC Test Machine Learning in Test Memory Test, Diagnosis, and Repair Multi-/Many-core Processor Test Online Test On-Chip Measurement Power/Thermal/Reliability Issues in Test Reconfigurable System Test Reliability and Testing for Emerging/Approximate/Quantum Computing RF Test Safety and Test for Automotive ICs Self-Repair SiP, Chiplet, 2.5D and 3D IC Test Software Test and Reliability Standards in Test System-on-Chip Test Test Compression Test Economics Test Quality Test Synthesis Test for Biomedical Circuits and Systems Test for MEMS and Microfluidic Systems Test for Nanoscale Devices and Emerging Technologies Test for Reversible and Quantum Circuits Test for Sensors and IoT Yield Analysis, Learning, and Enhancement
Last updated by Dou Sun on

Related Conferences

Related Journals

CCFFull NameImpact FactorPublisherISSN
IEEE Design & Test1.9IEEE2168-2356
CKnowledge-Based Systems7.2Elsevier0950-7051
CFuture Generation Computer Systems5.9Elsevier0167-739X
CNeurocomputing6.5Elsevier0925-2312
CPattern Recognition Letters3.9Elsevier0167-8655
CIEEE Transactions on Industrial Informatics11.7IEEE1551-3203
CIEEE Internet of Things Journal8.9IEEE2327-4662
CEngineering Applications of Artificial Intelligence9.0Elsevier0952-1976
CExpert Systems with Applications7.5Elsevier0957-4174
CIEEE Transactions on Big Data5.7IEEE2332-7790

Comments 0

No comments yet.

Please Login to post a comment