Conference Information
ATS 2020: Asian Test Symposium
Submission Date:
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Conference Date:
Penang, Malaysia
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Conference Location
Call For Papers
The Asian Test Symposium (ATS) provides an open forum dedicated to the electronic test of devices, boards, and systems—covering the complete test cycle from design verification, design-for-test, design-for-manufacturing, silicon debugging, manufacturing test, system test, diagnosis, reliability and failure analysis, and back to process and design improvement.

The main goal of IEEE Asian Test Symposium 2020 is to promote discussions and scientific exchange of knowledge between researchers, engineers, developers, academicians and students. ATS 2020 hopes to address design, test , validation methodologies and yield challenges faced by industry towards to industry 4.0 with collaboration efforts of academia,design tool and equipment suppliers, designers and test engineer.

The 29th IEEE Asian Test Symposium (ATS’20) is to be organized at Penang, Malaysia, during November 22-25, 2020.

The theme for the ATS 2020 is "Testing of internet-of-things in the era industry 4.0". The organizing committee of ATS 2020 invites you to Penang Island "Pearl of the orient".

The Asian Test Symposium (ATS) provides an open forum for researchers and industrial practitioners from all countries of the world to exchange innovative ideas on system, board, and device testing with design, manufacturing, and field consideration in mind.


Original papers on, but not limited to, the following areas are invited. 

    Analog/Mixed-Signal Test
    Automatic Test Generation
    Board Test and Diagnosis
    Boundary Scan Test
    Built-In Self-Test (BIST)
    Connectivity Testing
    Defect-Based Test
    Delay and Performance Test
    Dependability and Functional Safety
    Design for Test (DFT)
    Diagnosis and Silicon Debug
    Economic of Test
    Failure Analysis
    Fault Modeling and Simulation
    Fault Tolerance
    GPU Test
    Hardware-Oriented Security and trust
    High-Speed I/O Test
    Low-Power IC Test
    Machine Learning in Test
    Memory Test and Repair
    Multi-/Many-core Processor Test
    Online Test
    Power/Thermal/Reliability Issues in Test
    Reconfigurable System Test
    RF Test
    SiP, Stacked, 3D IC Test
    Standards in Test
    Test Compression
    Test for Biomedical Circuits and Systems
    Test for MEMS and Microfluidic Systems
    Test for Nanoscale Devices and Emerging Technologies
    Test for Reversible and Quantum Circuits
    Test for Sensors and IoT
    Test Quality
    Test Synthesis
    Validation and Verification
    Yield Analysis and Enhancement

Regular Sessions:

The ATS’20 Organizing Committee invites original, unpublished paper submissions on the above topics. Paper submission shall be complete manuscripts, not exceeding six pages in a standard IEEE two-column format. The submission will be considered evidence that upon acceptance the author(s) will submit a final camera-ready version of the paper for inclusion in the proceedings, and will present the paper at the symposium. Each accepted contribution must have at least one full paid registration by the time the camera ready paper is submitted for inclusion in the proceedings. ATS reserves the right to remove from IEEEXplore papers not presented at the symposium.

Paper Submission:

All submission should be made electronically in PDF format at ( A submission should contain a complete manuscript within a limit of 6 pages in 10-point single-spaced double-column format, and an abstract of 50-200 words. The paper must be submitted for blind review process. Once a submission is accepted, the author(s) must prepare the final camera-ready manuscript in time for inclusion in the proceedings, and present the paper at the symposium. In case of any difficulty in submission, authors may contact

Submission Link:
Last updated by Dou Sun in 2020-02-15
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