Topics — Original papers on, but not limited to, the following areas are invited:

    AI test and Test for AI
    Analog/Mixed-Signal Test
    ATE Design
    Automatic Test Pattern Generation (ATPG)
    Autonomous Testing
    Board-Level Testing and Diagnosis
    Boundary Scan Test
    Built-In Self-Test (BIST)
    CPU/GPU Test
    Connectivity Testing
    Defect-Based Test
    Delay and Performance Test
    Dependability and Functional Safety
    Design Verification, Validation, and Debug
    Design for Testability (DFT)
    Diagnosis and Silicon Debug
    Fault Diagnosis and Failure Analysis
    Fault Modeling and Simulation
    Fault Tolerance
    Hardware Oriented Security and Trust
    High-Speed I/O Test
    Heterogeneous Testing
    Low-Power IC Test
    Machine Learning in Test
    Memory Test, Diagnosis, and Repair
    Multi-/Many-core Processor Test
    Online Test
    On-Chip Measurement
    Power/Thermal/Reliability Issues in Test
    Reconfigurable System Test
    Reliability and Testing for Emerging/Approximate/Quantum Computing
    RF Test
    Safety and Test for Automotive ICs
    Self-Repair
    SiP, Chiplet, 2.5D and 3D IC Test
    Software Test and Reliability
    Standards in Test
    System-on-Chip Test
    Test Compression
    Test Economics
    Test Quality
    Test Synthesis
    Test for Biomedical Circuits and Systems
    Test for MEMS and Microfluidic Systems
    Test for Nanoscale Devices and Emerging Technologies
    Test for Reversible and Quantum Circuits
    Test for Sensors and IoT
    Yield Analysis, Learning, and Enhancement