Aims of the Conference:

ASP-DAC 2024 is the 29th annual international conference on VLSI design automation in Asia and South Pacific regions, one of the most active regions of design, CAD and fabrication of silicon chips in the world. The conference aims at providing the Asian and South Pacific CAD/DA and Design community with opportunities of presenting recent advances and with forums for future directions in technologies related to design and Electronic Design Automation (EDA). The format of the meeting intends to cultivate and promote an instructive and productive interchange of ideas among EDA researchers/developers and system/circuit/device designers. All scientists, engineers, and students who are interested in theoretical and practical aspects of VLSI design and design automation are welcomed to ASP-DAC. ASP-DAC recognizes excellent contributions with the Best Paper Award and 10-Year Retrospective Most Influential Paper Award. Selected papers will be invited to submit the extended version of their work to a Special Issue of Integration, the VLSI Journal.
Call for Papers ASP-DAC 2024

Areas of Interest:

Original papers in, but not limited to, the following areas are invited.

[1] System-Level Modeling and Design Methodology:
1.1. HW/SW co-design, co-simulation and co-verification
1.2. System-level design exploration, synthesis, and optimization
1.3. System-level formal verification
1.4. System-level modeling, simulation and validation
1.5. Networks-on-chip and NoC-based system design

[2] Embedded, Cyberphysical (CSP), IoT Systems and Software:
2.1. Many- and multi-core SoC architecture
2.2. IP/platform-based SoC design
2.3. Domain-specific architecture
2.4. Dependable architecture
2.5. Cyber physical system
2.6. Internet of things
2.7. Kernel, middleware, and virtual machine
2.8. Compiler and toolchain
2.9. Real-time system
2.10. Resource allocation for heterogeneous computing platform
2.11. Storage software and application
2.12. Human-computer interface

[3] Memory Architecture and Near/In Memory Computing:
3.1. Storage system and memory architecture
3.2. On-chip memory architectures and management: Scratchpads, compiler, controlled memories, etc.
3.3. Memory/storage hierarchies with emerging memory technologies
3.4. Near-memory and in-memory computing
3.5. Memory architecture and management for emerging memory technologies

[4] Tools and Design Methods with and for Artificial Intelligence (AI)
4.1. Design method for learning on a chip
4.2. Deep neural network for EDA
4.3. Tools and design methodologies for edge AI and TinyML
4.4. Efficient ML training and inference

[5] Hardware Systems and Architectures for AI:
5.1. Hardware, device, and architecture for deep neural networks
5.2. Systems-level design for (deep) neural computing
5.3. Neural network acceleration co-design techniques
5.4. Novel reconfigurable architectures including FPGAs for AI/MLs

[6] Photonic/RF/Analog-Mixed Signal Design:
6.1. Analog/mixed-signal/RF synthesis
6.2. Analog layout, verification, and simulation techniques
6.3. High-frequency electromagnetic simulation of circuit
6.4. Mixed-signal design consideration
6.5. Communication and computing using photonics

[7] Approximate, Bio-Inspired and Neuromorphic Computing:
7.1. Circuit and system techniques for approximate and stochastic computing
7.2. Neuromorphic computing
7.3. CAD for approximate and stochastic systems
7.4. CAD for bio-inspired and neuromorphic systems

[8] High-Level, Behavioral, and Logic Synthesis and Optimization:
8.1. High-level/Behavioral synthesis tool and methodology
8.2. Combinational, sequential and asynchronous logic synthesis
8.3. Synthesis for deep neural networks
8.4. Technology mapping, resource scheduling, allocation and synthesis
8.5. Functional, logic, and timing ECO (engineering change order)
8.6. Interaction between logic synthesis and physical design

[9] Physical Design and Timing Analysis:
9.1. Floorplanning, partitioning, placement and routing optimization
9.2. Interconnect planning and synthesis
9.3. Clock network synthesis
9.4. Post layout and post-silicon optimization
9.5. Package/PCB/3D-IC placement and routing
9.6. Extraction, TSV and package modeling
9.7. Deterministic/statistical timing analysis and optimization

[10] Design for Manufacturability/Reliability and Low Power:
10.1. Reticle enhancement, lithography-related design and optimization
10.2. Resilience under manufacturing variation
10.3. Design for manufacturability, yield, and defect tolerance
10.4. Reliability, robustness, aging and soft error analysis
10.5. Power modeling, analysis and simulation
10.6. Low-power design and optimization at circuit and system levels
10.7. Thermal aware design and dynamic thermal management
10.8. Energy harvesting and battery management
10.9. Signal/Power integrity, EM modeling and analysis

[11] Testing, Validation, Simulation, and Verification:
11.1. ATPG, BIST and DFT
11.2. System test and 3D IC test, online test and fault tolerance
11.3. Memory test and repair
11.4. RTL and gate-leveling modeling, simulation, and verification
11.5. Circuit-level formal verification
11.6. Device/circuit-level simulation tool and methodology

[12] Hardware and Embedded Security:
12.1. Hardware-based security
12.2. Detection and prevention of hardware trojans
12.3. Side-channel attacks, fault attacks and countermeasures
12.4. Design and CAD for security
12.5. Cyberphysical system security
12.6. Nanoelectronic security
12.7. Supply chain security and anti-counterfeiting
12.8. AI/ML security/privacy

[13] Emerging Devices, Technologies and Applications:
13.1. Quantum and Ising computing
13.2. Nanotechnology, MEMS
13.3. Biomedical, biochip, and biodata processing
13.4. Edge, fog and cloud computing
13.5. Energy-storage/smart-grid/smart-building design and optimization
13.6. Automotive system design and optimization
13.7. New transistor/device and process technology: spintronic, phase-change, single-electron etc.