Conference Information
NANOARCH 2016: ACM/IEEE International Symposium on Nanoscale Architectures
http://www.nanoarch.org/16/index.html
Submission Date:
2016-04-15
Notification Date:
2016-05-15
Conference Date:
2016-07-18
Location:
Beijing, China
Years:
12
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Conference Location
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Call For Papers
This 12th symposium will incorporate several exciting special sessions (e.g., beyond charge-based computing, benefits and challenges with emerging memory devices, and nanoelectronics for biomedical systems) and opportunities for interaction. In addition to Regular Papers (of up to 6 pages in length), we also invite 2-page Concept Papers in the area of nanofabrication, nano-computing, and emerging applications of nanosystems for presentation in Special Sessions. These concept papers would present lessdeveloped but radical and highly innovative work.

NANOARCH is the annual cross-disciplinary forum for the discussion of novel post-CMOS and advanced nanoscale CMOS directions. The symposium seeks papers on innovative ideas for solutions to the principal challenge facing integrated electronics in the 21st century how to design, fabricate, and integrate nanosystems to overcome the fundamental limitations of CMOS. In particular, such systems could as follow: (1) contain unconventional nanodevices with unique capabilities, including directions beyond simple switches, (2) introduce new logic and memory concepts, (3) involve novel circuit styles, (4) introduce new concepts for computing, (5) explore security architectures with nanotechnology, (6) reconfigure and/or mask faults at much higher rates than in CMOS, (7) involve new paradigms for manufacturing, and (8) rethink the methodologies and design tools involved.

Example topics (both theoretical and experimental) of interest include (but are not limited to):

    Nanoelectronic circuits, nanofabrics, computing paradigms and nanoarchitectures
    Paradigms and nanoarchitectures for computing with unpredictable devices
    Security architectures with nanofabrics
    Reliability aware computing
    3D hybrid nanoarchitectures
    2D/3D/hybrid nanodevice integration and manufacturing, with defect and fault tolerance
    Nanodevice and nanocircuit models, methodologies and computer aided design tools
    Fundamental limits of computing at the nanoscale 
Last updated by Dou Sun in 2016-02-27
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