Who publishes IEEE Micro?

IEEE Micro is published by IEEE.

What is the ISSN of IEEE Micro?

The ISSN of IEEE Micro is 0272-1732.

What is the impact factor of IEEE Micro?

The reported impact factor of IEEE Micro is 2.9. Impact factor values are reproduced from publishers and may lag the latest JCR release.

Journal Information

IEEE Micro

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Impact Factor:

2.9

Publisher:

IEEE

ISSN:

0272-1732

Viewed:

31646

Tracked:

12

Call For Papers

IEEE Micro is an academic journal published by IEEE. (ISSN 0272-1732, impact factor 2.9).

About IEEE Micro

IEEE Micro, a bimonthly publication of the IEEE Computer Society, reaches an international audience of microcomputer and microprocessor designers, system integrators, and users. Readers want to increase their technical knowledge and learn the latest industry trends.

Scope

IEEE Micro addresses users and designers of microprocessors and microprocessor systems, including managers, engineers, consultants, educators, and students involved with computers and peripherals, components and subassemblies, communications, instrumentation and control equipment, and guidance systems. Contributions should relate to the design, performance, or application of microprocessors and microcomputers. Tutorials, review papers, and discussions are also welcome. Sample topic areas include architecture, communications, data acquisition, control, hardware and software design/implementation, algorithms (including program listings), digital signal processing, microprocessor support hardware, operating systems, computer aided design, languages, application software, and development systems.

Last updated by Dou Sun in 2026-01-08

Special Issues

Special Issue on GenAI in the Age of Chiplets
Submission Date: 2026-08-02

Artificial Intelligence (AI) and Machine Learning (ML) have rapidly become foundational technologies driving innovation across science, industry, and society. Most recently, generative AI (including large language models, diffusion models, multimodal foundation models, and agentic systems enabled by generative models) has reshaped expectations for automation, creativity, and productivity. At the same time, the unprecedented scale, data movement, and energy demands of these models are straining traditional monolithic hardware designs and motivating a fundamental rethinking of system architectures.

Chiplet-based design has emerged as a compelling response to these challenges. By enabling 2.5D/3D heterogeneous integration, fine-grained technology scaling, and flexible composition of compute, memory, interconnect, and accelerators, chiplets offer a promising path toward scalable, cost-effective, and energy-efficient systems for generative AI. However, fully realizing this potential requires coordinated advances across the hardware–software stack, spanning architecture, packaging, interconnects, compilers, system software, and design methodologies.

This IEEE Micro Special Issue aims to bring together industrial practitioners and academic researchers to present visionary ideas, practical insights, and real-world experiences at the intersection of generative AI and chiplet-based systems. The issue will highlight key challenges, emerging solutions, and future directions for designing, building, and deploying GenAI platforms in the age of chiplets. We invite original contributions covering system-level, architectural, and microarchitectural aspects of generative AI platforms enabled by chiplets. Topics of interest include, but are not limited to:

    Chiplet Architectures for GenAI: 2.5D/3D chiplet architectures; wafer-scale systems; advanced packaging; heterogeneous and optical integration techniques for scalable GenAI.
    Interconnects and Memory Systems: High-bandwidth, low-latency interconnects; chiplet-to-chiplet and die-to-die communication; memory hierarchies and disaggregated memory for large model training and inference.
    Accelerators and Microarchitecture: Domain-specific accelerators and microarchitectural support for LLMs, multimodal models, training, fine-tuning, and inference.
    Hardware–Software Co-Design: Co-optimization of models, algorithms, hardware, and packaging; cross-layer design strategies for GenAI workloads; end-to-end full-stack AI solutions.
    Programming Models, Compilers, and Systems Software: Software stacks, compilers, runtime systems, and orchestration for large-scale deployment of generative AI on chiplet-based platforms.
    Reliability, Security, and Safety: Fault tolerance, reliability, and yield in chiplet systems; security, privacy, and robustness against adversarial threats in GenAI architectures.
    Energy Efficiency and Sustainability: Power- and energy-efficient architectures; thermal management; sustainability considerations for data center and mobile GenAI systems.
    AI for System Design: AI/ML techniques for fast system modeling, architecture exploration, design automation, and optimization of chiplet-based systems.
    Deployment Experiences and Case Studies: Lessons learned from commercially deployed GenAI systems, production chiplet platforms, and real-world workloads.

https://www.computer.org/digital-library/magazines/mi/cfp-gen-ai-age-chiplets

Last updated by Dou Sun in 2026-04-25

Best Papers

Year	Best Papers
2024	A Latency Processing Unit: A Latency-Optimized and Highly Scalable Processor for Large Language Model Inference
2018	Loihi: A Neuromorphic Manycore Processor with On-Chip Learning

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