ISLPED 2026 (International Symposium on Low Power Electronics and Design) is a CCF C / ICORE A / QUALIS A1 conference held in Chicago, Illinois, USA on 2026-08-05. The paper submission deadline is 2026-03-11 (extended). Acceptance notifications are sent on 2026-05-18.
The InternaKonal Symposium on Low Power Electronics and Design (ISLPED) is the premier venue for presenMng innovaMve research in all
aspects of low power electronics and design, including process technologies, analog/digital circuits, simulaMon and synthesis tools, AI/ML-
enhanced EDA/CAD, system-level design, opMmizaMon, system so_ware, and applicaMons. Specific topics include, but are not limited to, the
following three main tracks and sub-areas:
Track 1. Technology, Circuits, and Architecture
1.1. Technologies and Circuits
Low-power technologies for device, interconnect, logic, memory, 2.5/3D, cooling, harvesMng, sensors, opMcal, printable, biomedical, babery,
and alternaMve energy storage devices and technology enablers for non-Boolean and quantum/quantum-inspired compute models. Low-
power circuits for logic, memory, reliability, yield, clocking, resiliency; low-power analog/mixed-signal circuits for wireless, RF, MEMS,
ADC/DAC, I/O, PLLs/DLLs, DC-DC converters; energy-efficient circuits for emerging applicaMons (e.g., neuromorphic, biomedical, in-vitro
sensing, autonomous); circuits using emerging technologies; cryogenic circuits. DTCO for low power; combinatorial opMmizers (Ising
machine). AI/ML-based circuit opMmizaMon; circuit architecture for power-efficient AI applicaMons.
1.2. Logic and Architecture
Low-power logic and microarchitecture for SoC designs, processor cores (compute, graphics, and other special purpose cores), cache,
memory, arithmeMc/signal processing, cryptography, variability, asynchronous design, and non-convenMonal compuMng. System technology
co-opMmizaMon (STCO) for low power. AI/ML-assisted logic opMmizaMon and architecture exploraMon. Power efficient architecture for AI.
Track 2. EDA, Systems, and SoVware
2.1. CAD Tools and Methodologies
CAD tools, methodologies, and AI/ML-based approaches for low power and thermal-aware design (analog/digital). AI/ML for acceleraMon
of IP block design convergence. Power esMmaMon, opMmizaMon, reliability, and variaMon impact on power opMmizaMon at all levels of design
abstracMon: physical, circuit, gate, register transfer, behavior, and algorithm.
2.2. Systems and PlaXorms
Low-power, power-aware, and thermal-aware system design including data centers, SoCs, embedded systems, Internet-of-Things (IoT),
wearable compuMng, body-area networks, wireless sensor networks, and system-level power implicaMons due to reliability and variability.
ApplicaMons of AI/ML-based soluMons and brain-inspired compuMng to power-aware system and plajorm design.
2.3. SoVware and ApplicaKons
Energy-efficient, energy/thermal-aware so_ware and applicaMon design, including scheduling and management, power opMmizaMon
through HW/SW co-design, and emerging low-power AI/ML applicaMons.
2.4. Hardware and System Security
Low-power hardware security primiMves (PUF, TRNG, cryptographic/post-quantum cryptographic accelerators), nano-electronics security,
supply chain security, IoT security and AI/ML security; confidenMal compuMng; energy-efficient approaches to system security.
Track 3. AI/ML, Quantum and Emerging Hardware
3.1. Analog, Mixed-Signal & Emerging AI Hardware
Analog and mixed-signal compuMng architectures for AI/ML including analog matrix mulMplicaMon, in-memory compuMng, and compute-in-
memory techniques; emerging device technologies such as memristors, ReRAM, phase-change memory, and photonic compuMng;
neuromorphic and brain-inspired compuMng systems including spiking neural networks; circuit design techniques for analog AI accelerators
including ADC/DAC design, switched-capacitor networks, and noise-resilient architectures; EDA tools and methodologies for analog/mixed-
signal AI systems including simulaMon, verificaMon, and layout automaMon; process variaMon miMgaMon and robustness techniques for non-
ideal analog computaMon.
3.2. Digital AI Hardware & Systems
Digital accelerator architectures including systolic arrays, dataflow architectures, and tensor processing units; ASIC, FPGA, and GPU-based
implementaMons for AI/ML workloads; memory hierarchy design and opMmizaMon including high-bandwidth memory, scratchpads, and
cache architectures; sparse computaMon and quanMzaMon hardware; RTL design, verificaMon, and synthesis for AI accelerators; logic
synthesis, place-and-route, Mming closure, and power opMmizaMon for ML chips; system-level design including network-on-chip,
interconnects, and mulM-chip systems; compiler, runMme, and systems so_ware for AI hardware; performance modeling, simulaMon, and
design space exploraMon tools.
3.3. Quantum CompuKng and Emerging CompuKng Technologies
Quantum compuMng hardware plajorms including superconducMng qubits, trapped ions, and photonic systems; quantum algorithms, error
correcMon, and fault tolerance; quantum circuit compilaMon and opMmizaMon; NISQ algorithms and hybrid quantum-classical systems;
emerging post-CMOS paradigms including DNA compuMng, molecular compuMng, photonic compuMng, and probabilisMc compuMng;
neuromorphic and spin-based compuMng; EDA tools, programming frameworks, and benchmarking methodologies for quantum and
emerging compuMng plajorms.
Track 4. Industrial Design Track
This track solicits papers to reinforce interacMon between the academic research community and industry. Industrial Design track papers
have the same submission deadline as regular papers and should focus on similar topics but are expected to provide a complementary
perspecMve to academic research by focusing on challenges, soluMons, and lessons learnt while implemenMng industrial-scale designs.
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