Conference Information

Tau 2025: ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems

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Submission Date:
2025-01-13
Notification Date:
2025-02-24
Conference Date:
2025-05-01
Location:
Monterey, California, USA
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Call For Papers

Tau 2025 (ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems) is an academic conference held in Monterey, California, USA on 2025-05-01. The paper submission deadline is 2025-01-13. Acceptance notifications are sent on 2025-02-24.

It has become clear that timing analysis is NO longer a solved problem. So, what are new challenges as the industry embraces 5/3/2nm and below, rides the wave of ultra-low-power mobile, wearable devices and jumps on the IoT bandwagon? Are there new issues with older nodes, 14/28nm and up, in new design use cases? How do we model timing/power interactions? How do reliability requirements coming from ADAS/IoT and related impact timing? How to we apply AI/ML/Data Science techniques to the timing domain? How do we meet the insatiable demands for accuracy, performance and functionality? What new fundamental challenges are coming from process physics, 3D, variability, voltage sensitivity, analog effects, Quantum circuit modeling, Ising Models, Mixed signal modeling and validation? The TAU series of workshops provide an informal forum for practitioners and researchers working on these and other temporal aspects of analog and digital systems to disseminate early work and engage in a free discussion of ideas. On the thirty-first anniversary of the Tau series, the Tau 2025 workshop invites submissions and proposals from the traditional as well as emerging areas related to the timing properties of digital electronic systems, including but not limited to the topics listed below. Timing (including incremental timing) System-level timing Circuit/gate-level timing Transistor-level timing Timing of mixed signal circuits New types of latches, dual-edge devices, etc. Variability Timing analysis under variation and uncertainty Ultra-low voltage induced variation effects Statistical timing analysis and optimization Sensitivity/criticality analysis Yield analysis and optimization Characterization Efficient cell (library) characterization Variation effects and corner reductions Latch characterization Simulation and characterization of SRAM circuits Emerging technologies Full custom design analysis Special circuit families Timing issues for 3D ICs and TSVs New modeling techniques and machine learning Timing implications of emerging technologies Modeling and simulation Transistor level modeling Analog circuit modeling Circuit level simulation Qubit logic modeling Delay models and metrics Reliability modeling and simulation Power, trade-offs and optimization Timing issues in low-power design Power-delay tradeoffs Identifying timing criticality in presence of voltage drop/supply noise/variability Optimizing design in presence of non-constant supply (drop/noise/variability) Clocking Complex clock trees and networks Clocking, synchronization, and skew Clock domains, static/dynamic logic Novel clocking schemes Others Integrated functional-temporal analysis Formal theories and methods Asynchronous systems Smart sensor placement FPGA Design and Analysis
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