会议信息

PATMOS 2020: International Conference on Power and Timing Optimization and Simulatio

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截稿日期:
2020-04-15
通知日期:
2020-04-22
会议日期:
2020-07-13
会议地点:
Naples, Italy
届数:
30
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征稿

PATMOS 2020 (International Conference on Power and Timing Optimization and Simulatio) is an academic conference held in Naples, Italy on 2020-07-13. The paper submission deadline is 2020-04-15. Acceptance notifications are sent on 2020-04-22.

For almost 30 years, PATMOS has been one of the first conferences with a focus on low power. Starting in 2018, PATMOS will be collocated with two other conferences in closely related topics. Together, the well-established IOLTS and PATMOS as well as the upcoming IVSW, are forming the FEDfRo, the federative event on Design for Robustness. Registering to PATMOS will also allow visiting events from the other conference tracks. Thus, PATMOS will develop into a larger, better, full-grown three days event with more attractive shared keynotes and a larger common social program, connecting a larger community. PATMOS will not change at all, except for the conference time scheme. Topics of Interest Papers are solicited on, but not limited to, the following topics: Timing and Performance Methodologies and tools for the analysis, design and verification of timing and performance properties of integrated circuits and systems at all levels of abstraction Design for yield, design for manufacturability Simulation tools Designs and architectures for asynchronous circuits and systems Coupling effects: analysis, modelling, simulation & experimentation Low Power and Thermal-aware Design Power/Thermal-aware architectures Power and performance optimization of multi-core systems Design techniques for thermal-aware and low power circuits and systems Methods for power and thermal estimation and optimization Power/thermal-aware synthesis and floorplanning Energy-harvesting Low Power Systems: wireless sensor networks, mobile computing, IoT Compilers, operating systems and runtime systems Power efficiency through parallelizing compilers or parallel programming Methods for programming novel multi-core architectures Real-time system compilers, operating systems and run-time systems FPGAs and GPU-based accelerators Novel architectures for FPGAs and GPU-based accelarators High-Level abstractions and CAD tools Neuro-Inspired accelerators Customized processor instruction sets Optimization techniques for dynamically reconfigurable systems Case studies and challenges High Performance Computing (HPC) and Data Centers Supercomputing: compilers, operating systems, run time systems Hardware-software interaction for low power and high-performance Modeling and analysis of energy costs for HPC systems and infrastructures Power analysis for data centers, supercomputers, communication networks Power-efficient I/O interfaces and NoC design Case studies: test cases, or design study challenges on data stations or supercomputers Application-specific power efficiency by algorithmic and analytic efforts Application of Computational Intelligence to implement high-performance systems (Neural Networks, Support Vector Machines, Self-Organizing Maps, Neuromorphic systems) Banking, financial modelling and financial database acceleration Social networks, games, entertainment, ambient intelligence, ubiquitous and wearable computing Bioinformatics, bio-inspired, medical, and genetics systems and life sciences Physics and astronomy, weather prediction, oil and gas exploration. Security systems, cryptography, object recognition and tracking, global navigation satellite systems Audio/video, imaging, smart cameras, PDAs, smart image sensors, Reconfigurable Video Coding (RVC), etc. Aerospace, avionics, automotive and railway, and many other application areas Design for aging Aging effects and their impact on circuits Aging-aware models Aging-aware timing and power analysis Circuit aging prediction Aging-aware design
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