会议信息

ASP-DAC 2027: Asia and South Pacific Design Automation Conference

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截稿日期:
2026-07-11 已截稿
通知日期:
2026-09-04
会议日期:
2027-01-25
会议地点:
Tokyo, Japan
届数:
32
CCF: C   ICORE: B   QUALIS: A2   浏览: 250930   关注: 89   参加: 8
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会伴指数 (CP-I)

75.9 / 100
全站第 255 名 / 共 5,759 个会议 · 前 5%

机器人与控制 第 6 / 478 系统与体系结构 第 48 / 341

学术认可 (35%)
92
投稿选择性 (20%) 无数据 —— 按中性基准 50 分计入 —
会议传承 (20%)
94
社区关注 (10%)
74
资料公开度 (15%)
50

用到的输入: 收录等级：CCF C, ICORE B, QUALIS A2 · 有据可查的届次：32 · 在会伴关注它的研究者：89 人 · 过去 24 个月打开过本页的研究者：58 人

公开资料里还缺: 历年录用率 (+4.5) · 历届信息 (+3.0)
主办方认领本会议后，可直接在这一页补上；分数每晚重算。如何提升这个分数

置信度 80% —— 分数中有多大比例来自实际观测到的数据，而不是中性基准。 这个分数是怎么算出来的 · 查看完整榜单 · 算法版本 1.2 · 算于 2026-10-25

征稿

ASP-DAC 2027 (Asia and South Pacific Design Automation Conference) is a CCF C / ICORE B / QUALIS A2 conference held in Tokyo, Japan on 2027-01-25. The paper submission deadline is 2026-07-11 (extended). Acceptance notifications are sent on 2026-09-04.

Aims of the Conference: ASP-DAC 2027 is the 32nd annual international conference on VLSI design automation in Asia and South Pacific regions, one of the most active regions of design, CAD, and fabrication of silicon chips in the world. The conference aims to provide the Asian and South Pacific CAD/DA and Design community with opportunities to present recent advances and with forums for future directions in technologies related to design and Electronic Design Automation (EDA). The format of the meeting intends to cultivate and promote an instructive and productive interchange of ideas among EDA researchers/developers and system/circuit/device designers. All scientists, engineers, and students who are interested in theoretical and practical aspects of VLSI design and design automation are welcomed to ASP-DAC. ASP-DAC recognizes excellent contributions with the Best Paper Award and 10-Year Retrospective Most Influential Paper Award. Areas of Interest: Original papers in, but not limited to, the following areas are invited. 1 System-Level Modeling and Design Methodology: 1.1. HW/SW co-design, co-simulation and co-verification 1.2. System-level design exploration, synthesis, and optimization 1.3. System-level formal verification 1.4. System-level modeling, simulation and validation 1.5. Networks-on-chip and NoC-based system design 2 Embedded, Cyberphysical (CPS), IoT Systems, and Software: 2.1. Many- and multi-core SoC architecture 2.2. IP/platform-based SoC design 2.3. Real-time systems/Dependable architecture 2.4. Cyber-physical systems and Internet of Things 2.5. Kernel, middleware, and virtual machine 2.6. Compiler and toolchain 2.7. Resource allocation for heterogeneous computing platform 2.8. Storage software and application 3 Memory Architecture and Near/In Memory Computing: 3.1. Storage system and memory architecture 3.2. On-chip memory architectures and management: Scratchpads, compiler, controlled memories, etc. 3.3. Memory/storage hierarchies and management for emerging memory technologies 3.4. Near-memory and in-memory computing 4 Tools and Methods for Building Artificial Intelligence (AI): 4.1. Design method for learning on a chip 4.2. Tools and design methodologies for edge AI and TinyML 4.3. Efficient ML training and inference Note: papers on AI/LLM-assisted tools and design methods should be submitted to respective tracks 5 Hardware Systems and Architectures for AI: 5.1. Hardware, device, architecture, and system-level design for deep neural networks 5.2. Hardware acceleration for LLM 5.3. Neural network acceleration co-design techniques 5.4. Novel reconfigurable architectures, including FPGAs for AI/MLs 6 Photonic/RF/Analog-Mixed Signal Design: 6.1. Photonic/RF/Analog-mixed-signal synthesis, layout, and verification 6.2. High-frequency electromagnetic and circuit simulations 6.3. Mixed-signal design consideration 6.4. Communication and computing using photonics 7 Approximate, Bio-Inspired and Neuromorphic Computing: 7.1. Circuit and system techniques for approximate, hyper-dimensional, and stochastic computing 7.2. Neuromorphic computing 7.3. CAD for approximate and stochastic systems 7.4. CAD for bio-inspired and neuromorphic systems 8 High-Level, Behavioral, and Logic Synthesis and Optimization: 8.1. High-level/Behavioral synthesis tool and methodology 8.2. Combinational, sequential, and asynchronous logic synthesis 8.3. Synthesis for deep neural networks 8.4. Technology mapping, resource scheduling, allocation and synthesis 8.5. Functional, logic, and timing ECO (engineering change order) 8.6. Interaction between logic synthesis and physical design 9 Physical Design and Timing Analysis: 9.1. Floorplanning, partitioning, placement and routing optimization 9.2. Interconnect planning and synthesis 9.3. Clock network synthesis 9.4. Post-layout and post-silicon optimization 9.5. Package/PCB/3D-IC placement and routing 9.6. Extraction, TSV, and package modeling 9.7. Deterministic/statistical timing analysis and optimization 10 Design for Manufacturability/Reliability and Low Power: 10.1. Reticle enhancement, lithography-related design and optimization 10.2. Design for manufacturability, yield, and defect tolerance 10.3. Reliability, robustness, aging, and soft error analysis 10.4. Power modeling, analysis and simulation 10.5. Low-power design and optimization at circuit and system levels 10.6. Thermal-aware design and dynamic thermal management 10.7. Energy harvesting and battery management 10.8. Signal/Power integrity, EM modeling and analysis 11 Testing, Validation, Simulation, and Verification: 11.1. ATPG, BIST and DFT 11.2. System test and 3D IC test, online test and fault tolerance 11.3. Memory test and repair 11.4. RTL and gate-leveling modeling, simulation, and verification 11.5. Circuit-level formal verification 11.6. Device/circuit-level simulation tool and methodology 12 Hardware and Embedded Security: 12.1. Hardware-based security 12.2. Detection and prevention of hardware trojans 12.3. Side-channel attacks, fault attacks and countermeasures 12.4. Design and CAD for security 12.5. Cyberphysical system security 12.6. Nanoelectronic security 12.7. Supply chain security and anti-counterfeiting 12.8. Security/privacy for LLM/AI/ML 13 Emerging Devices, Technologies and Applications: 13.1. EDA and circuits design for quantum and Ising computing 13.2. Nanotechnology, MEMS 13.3. Biomedical, biochip, and biodata processing 13.4. Edge, fog and cloud computing 13.5. Automotive and smart-energy systems design and optimization 13.6. New device and process technologies Authors must submit full-length, double-columned, original papers, with a maximum of 6 pages in PDF format (including the abstract, figures and tables). One page of references is allowed, which does not count towards the 6-page limitation. ASP-DAC does not allow double and/or parallel submissions of similar work to any other conferences, symposia, or journals. Extended abstracts published elsewhere may be submitted but must include sufficient new content. The submission must not include information that serves to identify the authors of the manuscript, such as name(s) or affiliation(s) of the author(s), anywhere in the manuscript, abstract, references, and bibliographic citations. While research papers with open-source software are highly encouraged where the software will be made publicly available (via GitHub or similar), the authors' identities need to be anonymized in the submitted paper for the double-blind review process. Issuing the paper as a technical report, posting the paper on a website, or presenting the paper at a workshop that does not publish formally reviewed proceedings does not disqualify it from appearing in the proceedings. Note that each paper shall be accompanied by at least one different conference registration at the speaker's registration rate. ACM and IEEE reserve the right to exclude a paper from distribution after the conference (e.g., removal from ACM Digital Library and IEEE Xplore) if the paper is not presented at the conference by any author.
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最佳论文

年份最佳论文
2023Rethink before Releasing Your Model: ML Model Extraction Attack in EDA
2023Approximate Floating-Point FFT Design with Wide Precision-Range and High Energy Efficiency
2020Towards Area-Efficient Optical Neural Networks: An FFT-based Architecture
2020Equivalent Capacitance Guided Dummy Fill Insertion for Timing and Manufacturability
2019GraphSAR: A Sparsity-Aware Processing-in-Memory Architecture for Large-Scale Graph Processing on ReRAMs
2019Energy-Efficient, Low-Latency Realization of Neural Networks through Boolean Logic Minimization
2018Process Variation Aware Data Management for Magnetic Skyrmions Racetrack Memory
2017Classification Accuracy Improvement for Neuromorphic Computing Systems with One-level Precision Synapses
2017Spendthrift: Machine Learning Based Resource and Frequency Scaling for Ambient Energy Harvesting Nonvolatile Processors
2016Lattice-Based Boolean Diagrams: Canonical, Order-Independent Graphical Representations of Boolean Functions
2016Netlist Reverse Engineering for High-Level Functionality Reconstruction
2015Quantitative Modeling of Racetrack Memory, A Tradeoff among Area, Performance, and Power
2014Flexible Packed Stencil Design with Multiple Shaping Apertures for E-Beam Lithography
2013I-LUTSim: An Iterative Look-Up Table Based Thermal Simulator for 3-D Ics
2013A Case for Wireless 3D NoCs for CMPs
2012An Intelligent Analysis of Iddq Data for Chip Classification in Very Deep-Submicron (VDSM) CMOS Technology
2012EPIC: Efficient Prediction of IC Manufacturing Hotspots With A Unified Meta-Classification Formulation
2011Co-Design of Cyber-Physical Systems via Controllers with Flexible Delay Constraints
2010SCGPSim: a fast SystemC simulator on GPUs
2010A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography
2009Efficiently finding the 'best' solution with multi-objectives from multiple topologies in topology library of analog circuit
2009FastYield: variation-aware, layout-driven simultaneous binding and module selection for performance yield optimization
2008Variability-driven module selection with joint design time optimization and post-silicon tuning
2008An efficient, fully nonlinear, variability-aware non-monte-carlo yield estimation procedure with applications to SRAM cells and ring oscillators
2007Protocol Transducer Synthesis using Divide and Conquer approach
2007A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects
2006Post-routing redundant via insertion for yield/reliability improvement
2006Constraint-driven bus matrix synthesis for MPSoC
2005Speed and voltage selection for GALS systems based on voltage/frequency islands
2005Fast PLL simulation using nonlinear VCO macromodels for accurate prediction of jitter and cycle-slipping due to loop non-idealities and supply noise
2005The polygonal contraction heuristic for rectilinear Steiner tree construction
2004Representative frequency for interconnect R(f)L(f)C extraction
2004Preserving synchronizing sequences of sequential circuits after retiming
2003Design of a scalable RSA and ECC crypto-processor
2003Statistical delay computation considering spatial correlations
2003Towards on-chip fault-tolerant communication
2002Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing
2001Correlation method of circuit-performance and technology fluctuations for improved design reliability
2001Design rewiring based on diagnosis techniques
2000A cell synthesis method for salicide process
2000Delay-optimal wiring plan for the microprocessor of high performance computing machines
2000Circuit performance oriented device optimization using BSIM3 pre-silicon model parameters
1998Concurrent Technology, Device, and Circuit Development for EEPROMs
1998On the CSC Property of Signal Transition Graph Specifications for Asynchronous Circuit Design
1995Power Analysis of a 32-bit Embedded Microcontroller
1995Maple-opt: A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Performance Optimization

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