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NANOARCH 2016: ACM/IEEE International Symposium on Nanoscale Architectures

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NANOARCH
투고 마감일:
2016-04-15
통보일:
2016-05-15
개최일:
2016-07-18
개최지:
Beijing, China
개최 횟수:
12
조회: 18586   팔로우: 1   참가: 0

논문 모집

NANOARCH 2016 (ACM/IEEE International Symposium on Nanoscale Architectures) is an academic conference held in Beijing, China on 2016-07-18. The paper submission deadline is 2016-04-15. Acceptance notifications are sent on 2016-05-15.

This 12th symposium will incorporate several exciting special sessions (e.g., beyond charge-based computing, benefits and challenges with emerging memory devices, and nanoelectronics for biomedical systems) and opportunities for interaction. In addition to Regular Papers (of up to 6 pages in length), we also invite 2-page Concept Papers in the area of nanofabrication, nano-computing, and emerging applications of nanosystems for presentation in Special Sessions. These concept papers would present lessdeveloped but radical and highly innovative work. NANOARCH is the annual cross-disciplinary forum for the discussion of novel post-CMOS and advanced nanoscale CMOS directions. The symposium seeks papers on innovative ideas for solutions to the principal challenge facing integrated electronics in the 21st century how to design, fabricate, and integrate nanosystems to overcome the fundamental limitations of CMOS. In particular, such systems could as follow: (1) contain unconventional nanodevices with unique capabilities, including directions beyond simple switches, (2) introduce new logic and memory concepts, (3) involve novel circuit styles, (4) introduce new concepts for computing, (5) explore security architectures with nanotechnology, (6) reconfigure and/or mask faults at much higher rates than in CMOS, (7) involve new paradigms for manufacturing, and (8) rethink the methodologies and design tools involved. Example topics (both theoretical and experimental) of interest include (but are not limited to): Nanoelectronic circuits, nanofabrics, computing paradigms and nanoarchitectures Paradigms and nanoarchitectures for computing with unpredictable devices Security architectures with nanofabrics Reliability aware computing 3D hybrid nanoarchitectures 2D/3D/hybrid nanodevice integration and manufacturing, with defect and fault tolerance Nanodevice and nanocircuit models, methodologies and computer aided design tools Fundamental limits of computing at the nanoscale
최종 수정: Dou Sun ()

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관련 저널

CCF정식 명칭영향력 지수출판사ISSN
AIEEE Transactions on Multimedia9.7IEEE1520-9210
CKnowledge-Based Systems7.2Elsevier0950-7051
BSoftware & Systems Modeling3.2Springer1619-1366
AIEEE Transactions on Computers3.8IEEE0018-9340
CFuture Generation Computer Systems6.1Elsevier0167-739X
CNeurocomputing6.5Elsevier0925-2312
CPattern Recognition Letters3.9Elsevier0167-8655
BPattern Recognition7.6Elsevier0031-3203
IEEE Access3.6IEEE2169-3536
AIEEE Transactions on Dependable and Secure Computing7.5IEEE1545-5971

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