Conference Information

ISQED 2026: International Symposium on Quality Electronic Design

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Submission Date:
2025-11-17 Extended
Notification Date:
2026-01-22
Conference Date:
2026-04-08
Location:
San Francisco, California, USA
Years:
27
QUALIS: b1   Viewed: 106540   Tracked: 2   Attend: 0

Call For Papers

ISQED 2026 (International Symposium on Quality Electronic Design) is a QUALIS B1 conference held in San Francisco, California, USA on 2026-04-08. The paper submission deadline is 2025-11-17 (extended). Acceptance notifications are sent on 2026-01-22.

A pioneer and leading multidisciplinary conference, ISQED accepts and promotes papers related to the manufacturing, design and EDA. Authors are invited to submit papers in the various disciplines of high level design, circuit design (digital, analog, mixed-signal, RF), test & verification, design automation tools; processes; flows, device modeling, semiconductor technology, advance packaging, and biomedical & bioelectronic devices. All past Conference proceedings & Papers have been published in IEEE Xplore digital library and indexed by Scopus. The details of various topics of paper submission are as follows: EDA Tools and Methodologies & Agentic AI (EDA) Agentic AI for Electronic Design and Design Automation (AI): Systems and hardware enabling autonomous, goal-driven AI agents, including cognitive computing, neuromorphic architectures, and secure AI accelerators. Covering design, implementation, and applications in intelligent interaction and cognitive environments. EDA tools, design flows, and physical design methodologies for digital, analog, and mixed-signal systems Tools for analyzing and mitigating variation, aging effects, and soft errors Design, verification, and maintenance of hard and soft IP blocks Integration, testing, qualification, and manufacturing of IP from diverse vendors EDA tools for emerging application domains such as smart power grids and renewable energy systems Design automation methodologies for 3D ICs, heterogeneous integration, and advanced packaging Modeling and simulation of semiconductor devices and processes (TCAD) CAD techniques for bio-inspired and neuromorphic computing systems EDA tools and methods for photonic devices, circuit, and system design EDA for MEMS and other micro/nano-scale systems Other topics related to design automation tools, platforms, and methodologies Hardware and System Security (HSS) Attacks and countermeasures, including side-channel attacks, reverse engineering, hardware Trojans, and physical tampering Hardware-based security primitives such as physically unclonable functions (PUFs), true random number generators (TRNGs), and lightweight cryptographic ciphers Security, privacy, and trust protocols; secure information flow; and trusted execution environments Trust establishment using untrusted tools, third-party IP, AI/ML models, and fabrication/manufacturing services Secure hardware architectures and memory systems Post-quantum cryptographic and security primitives for hardware platforms Security challenges and design opportunities in emerging nanoscale devices and technologies Internet of Things (IoT) and cyber-physical system (CPS) security at the hardware and system levels Other topics related to hardware, embedded, and system-level security Design Test and Verification (DTV) Formal, assertion-based, simulation-based, and hybrid verification techniques for hardware and software systems Design-for-Testability (DFT), Automatic Test Equipment (ATE), and Built-In Self-Test (BIST) for digital, analog/mixed-signal, SoC, and memory components Test synthesis and synthesis-for-testability for improved coverage and quality Fault diagnosis, IDDQ testing, novel test methods, fault modeling, ATPG, and DPPM prediction SoC and IP testing strategies, including hierarchical and system-level test approaches Design methodologies linking testability to manufacturing and yield improvement Hardware/software co-verification and co-validation strategies Advanced verification methodologies and testbenches, including UVM, HDLs, and HVLs Formal and semi-formal validation techniques supporting functional safety and security Self-checking testbenches and novel methods for analog/mixed-signal verification Any other emerging topics related to design test and verification Emerging Device and Process Technologies and Applications (EDPT) Design, simulation, and modeling of emerging solid-state devices and materials Emerging non-volatile memory and logic technologies, such as STT-RAM, PC-RAM, RRAM, and memristors Applications of emerging devices in advanced computing domains including cognitive, neuromorphic, and quantum computing Qubit technologies and quantum circuits for quantum information processing Specialty device technologies, including MEMS, NEMS, and other nanoelectronic devices Design-Technology Co-Optimization (DTCO) methodologies across ASIC, FPGA, RF, memory, and custom/semi-custom designs Advanced-node manufacturing techniques, including EUV lithography, DSA, and multiple patterning Advanced interconnect solutions such as air-gap structures and silicon photonics Modeling and optimization of emerging technology impact on power, performance, area, cost, and reliability Design methods and tools for improving yield, manufacturability, and process robustness Other topics relevant to emerging device, process, and integration technologies Circuit Design, 3D Integration and Advanced Packaging (ICAP) Low-power, high-performance, and reliable design of digital, analog, RF, memory, interconnect, programmable logic, and FPGA circuits Techniques for leakage reduction, dynamic/static power optimization, and power management Analog and mixed-signal circuit design, including all-digital PLLs/DLLs, ADCs, and DACs Adaptive and resilient circuit techniques for variability and fault tolerance On-chip sensors and monitors for process, voltage, temperature, and aging variations Hardware design for IoT systems, including digital logic, memory, wireless interfaces, energy harvesting, signal processing, and power management Advanced packaging technologies including 3D ICs, 2.5D interposers, and multi-chip modules and their impact on design methodologies Design techniques and flows for vertically integrated circuits and chips Modeling and mitigation of inter-die and inter-layer interactions in 3D ICs Design of die-to-die and chip-to-chip interfaces for 2.5D/3D integration Design-for-testability, yield enhancement, and system-level design considerations in 3D/2.5D ICs Die-package co-design and integration challenges Other topics related to circuit design, 3D integration, and advanced packaging technologies System-level Design and Methodologies (SDM) Design methods for complex systems including multi-core processors, embedded systems, SoCs, GPUs, accelerators, and heterogeneous architectures System-level trade-off analysis and multi-objective optimization (e.g., yield, power, performance, area, and cost) Power and thermal management techniques at the system level Modeling and simulation frameworks to assess the impact of process, voltage, temperature, and aging variations on system performance and reliability System-level implications and integration of emerging technologies Cyber-Physical Systems (CPS): design methodologies, tools, and reliability analysis Hardware/software co-design, co-simulation, co-optimization, and design-space exploration Prototyping and emulation of hardware/software systems using FPGAs Microarchitectural transformations and optimization techniques System communication and interconnect architecture, including Network-on-Chip (NoC) methodologies Application-driven design of heterogeneous computing platforms Any other topics related to system-level design, modeling, and co-optimization Cognitive Computing Hardware (CCH) Neuromorphic computing, non-Von Neumann architectures, and brain-inspired hardware paradigms Hardware and architectures for neural networks, including deep learning and spiking neural networks Neural network acceleration using GPGPUs, FPGAs, dedicated ASICs, and custom silicon Cognitive-inspired computing systems and fundamentals for intelligent information processing AI-assisted cognitive computing methods and hardware/software co-design approaches Hardware support for secure and reliable machine learning and cognitive applications Cognitive computing in large-scale systems: big data processing, sensing, and interaction Brain analysis and neuroscience-driven models for hardware design Internet of Cognitive Things, cognitive environments, and data-driven sensing systems Cognitive robots, intelligent agents, and edge intelligence platforms Security and trust challenges in cognitive-inspired computing systems Testbeds, prototype implementations, and emerging applications of cognitive hardware Other topics related to cognitive and intelligent computing hardware
Last updated by Dou Sun in

Best Papers

YearBest Papers
2010UC-PHOTON: A novel hybrid photonic network-on-chip for multiple use-case applications
2009Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design
2009Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay
20093D-GCP: An analytical model for the impact of process variations on the critical path delay distribution of 3D ICs
2008Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)
2008A Methodology for Characterization of Large Macro Cells and IP Blocks Considering Process Variations
2008Characterization of Standard Cells for Intra-Cell Mismatch Variations
2007Design of a Window Comparator with Adaptive Error Threshold for Online Testing Applications
2007A DOE Set for Normalization-Based Extraction of Fill Impact on Capacitances
2007Assessing the Implications of Process Variations on Future Carbon Nanotube Bundle Interconnect Solutions
2006FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs
2006System-Level SRAM Yield Enhancement
2006Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO)
2006Power Gating with Multiple Sleep Modes
2005A Min-Variance Iterative Method for Fast Smart Dummy Feature Density Assignment in Chemical-Mechanical Polishing
2005Noise Library Characterization for Large Capacity Static Noise Analysis Tools
2005A New Method for Design of Robust Digital Circuits
2005A Mask Reuse Methodology for Reducing System-on-a-Chip Cost
2004Application Specific Worst Case Corners Using Response Surfaces and Statistical Models
2004Scan BIST Targeting Transition Faults Using a Markov Source
2004SRAM Leakage Suppression by Minimizing Standby Supply Voltage
2004Robustness Enhancement through Chip-Package Co-Design for High-Speed Electronics
2003Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact on On-Chip Interconnect Delay
2002Pre-route Noise Estimation in Deep Submicron Integrated Circuits
2001Color Counting and its Application to Path Delay Fault Coverage
2001A System for Automatic Recording and Prediction of Design Quality Metrics
2000Synthesis Experiments and Performance Metrics for Evaluating the Quality of IP Blocks and Megacells
2000On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques
2000Quick On-Chip Self- and Mutual-Inductance Screen

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