DVCon Europe 2020 (The Design and Verification Conference in Europe) is an academic conference held in Munich, Germany on 2020-10-27. The paper submission deadline is 2020-05-11 (extended). Acceptance notifications are sent on 2020-09-14.
The Design and Verification Conference & Exhibition Europe (DVCon Europe) is the premier European technical conference on system, software, design, verification, validation or integration. It is a place where the latest methodologies and technologies for the industrial use of tools, languages, and standards for integrated and embedded systems and products are shared and discussed.
The conference covers the application of standards, methodologies, and flows for system-level, hardware and software design, verification, validation, design automation and IP reuse.
Industry applications of interest include (but not limited to) automotive, mobile communication, aerospace, healthcare, chip-cards, consumer and power electronics. DVCon Europe solicits submissions related to advanced design and verification on special interest areas such as Digital Twin, Machine Learning, Internet-of-things, Functional safety and security, AI, ADAS and digitalization.
DVCon Europe 2020 accepts submissions of papers, tutorials and panels with highly technical content reflecting real life experiences. The following are example topics.
SYSTEM-LEVEL AND SOFTWARE DESIGN
Virtual prototyping and Digital Twins
Transaction-level modeling (e.g., SystemC TLM)
Hardware-assisted prototyping
Hardware/software/embedded co-design
Machine Learning
MODEL-BASED AND MODEL SUPPORTED SOFTWARE DESIGN
Software for verification
Software development and verification
Model based software design
Low level software design and verification
Model based tools and techniques for application level software.
VERIFICATION & VALIDATION
Verification process, reuse and resource management
Methods bridging between verification and validation
Hardware/software co-verification
Advanced methodologies, testbenches, and flows (e.g., UVM, HDLs, HVLs)
Formal and semi-formal V&V techniques
IP REUSE & DESIGN AUTOMATION
High-level synthesis from ESL languages
Interoperability of models and/or tools
IP tagging, protection or security
SoC and IP integration methods, flows, and tools
Configuration management of IPs including different abstraction level
Flow and tool automation (e.g., IP-XACT)
FUNCTIONAL SAFETY AND SECURITY
Methods and flows for functional safety standard compliance (e.g., ISO 26262, DO-254)
Safety and security in verification and validation
Requirements-driven design and verification including traceability
New methods and tools supporting functional safety and security
MIXED-SIGNAL AND LOW-POWER DESIGN AND VERIFICATION
AMS modeling for concept and system-level design
Application of mixed-signal extensions in verification (e.g., UVM-MS)
Real-number modeling approaches
Self-checking testbenches in analog verification
Low-power design and verification (e.g., UPF)
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