Conference Information
HEART 2017 : International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies
http://www.cs.tsukuba.ac.jp/~yoshiki/heart/HEART2017/
Submission Date:
2017-02-20
Notification Date:
Conference Date:
2017-06-07
Location:
Bochum, Germany
Years:
8
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Conference Location
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Call For Papers
The Seventh International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART) is a forum to present and discuss new research on accelerators and the use of reconfigurable technologies for high-performance and/or power-efficient computation. Submissions are solicited on a wide variety of topics related to the acceleration for high-performance computation, including but not limited to:

    Architectures and systems:
        Novel systems/platforms for efficient acceleration based on FPGA, GPU, and other devices
        Heterogeneous processor architectures and systems for scalable, high-performance, high-reliability, and/or low-power computation
        Reconfigurable and configurable hardware and systems including IP-cores, embedded systems, SoCs, and cluster/grid/cloud computing systems for scalable, high-performance and/or low-power processing
        Custom computing system for domain-specific applications such as Big-data, multimedia, bioinformatics, cryptography, and more
        Novel architectures and device technologies that can be applied to efficient acceleration, including many-core/NoC architectures, 3D-stacking technologies and optical devices
    Software and applications:
        Novel applications of high-performance computing and Big-data processing with efficientacceleration and custom computing
        System software, compilers and programming languages for efficient accelerationsystems / platforms, including many-core processors, GPUs, FPGAs and otherreconfigurable /custom processors
        Run-time techniques for acceleration, including Just-in-Time compilation and dynamicpartial-reconfiguration
        Performance evaluation and analysis for efficient acceleration
        High-level synthesis and design methodologies for heterogeneous, reconfigurable and/orcustom processors/systems

In order to encourage open discussion on future directions, the program committee will provide higher priority for papers that present highly innovative and challenging ideas.

We are planning to organize special sessions on HPC, Big data, and Dynamic Reconfiguration. When submitting a paper, please select topic(s) if the paper is related to them. Note that regardless of the selection of special session topic(s), your paper will undergo the same peer-review process as the main technical track.

As in previous HEART editions, we plan to publish selected accepted papers at HEART 2017 in post-proceedings ACM SIGARCH Computer Architecture News (CAN), which is also available in ACM Digital Library.

Prospective authors are invited to submit original and unpublished contributions as 6-page papers to be considered as regular papers or 4-page papers to be considered as poster papers. All contributions must be submitted electronically in PDF format (two columns, US letter size, single-spacing, 10 points for main body text). For double-blind review, manuscripts must NOT identify the authors in any way, so author names, affiliations, e-mail addresses and self-references should be blanked out. Papers that identify authors may be rejected without review.

Each accepted paper MUST have at least one author with a regular registration for the manuscript to be included and published in the symposium proceedings and ACM SIGARCH CAN post-proceedings. Authors are also expected to attend and present their paper(s) at the symposium.

The HEART2017 paper template can be download here: HEART2017 template in MS-Word, HEART2017 template in Latex.
Last updated by Dou Sun in 2017-01-07
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