会议信息

DFT 2025: International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

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DFT
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截稿日期:
2025-04-27
通知日期:
2025-07-08
会议日期:
2025-10-21
会议地点:
Barcelona, Spain
届数:
38
QUALIS: B1   浏览: 21036   关注: 2   参加: 1

会伴指数 (CP-I)

64.2 / 100
全站第 453 名 / 共 5,647 个会议 · 前 9%

材料、机械与制造 第 1 / 261 系统与体系结构 第 78 / 340

学术认可 (35%)
78
投稿选择性 (20%) 无数据 —— 按中性基准 50 分计入 —
会议传承 (20%)
99
社区关注 (10%)
19
资料公开度 (15%)
35

用到的输入: 收录等级：QUALIS B1 · 有据可查的届次：38 · 在会伴关注它的研究者：2 人 · 过去 24 个月打开过本页的研究者：2 人

公开资料里还缺: 历年录用率 (+4.5) · 历届信息 (+3.0) · 最佳论文记录 (+2.3)
主办方认领本会议后，可直接在这一页补上；分数每晚重算。如何提升这个分数

置信度 80% —— 分数中有多大比例来自实际观测到的数据，而不是中性基准。 这个分数是怎么算出来的 · 查看完整榜单 · 算法版本 1.1 · 算于 2026-09-03

征稿

DFT 2025 (International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems) is a QUALIS B1 conference held in Barcelona, Spain on 2025-10-21. The paper submission deadline is 2025-04-27. Acceptance notifications are sent on 2025-07-08.

DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies, RISC-V architectures and AI-based solutions. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, availability, and security that are affected by defects during manufacturing and by faults during system operation are of interest. Topics include (but are not limited to) the following: 1. Yield Analysis and Modeling Advanced yield models, defect/fault analysis, statistical modeling, and critical area analysis. 2. Testing Techniques Innovative testing methodologies for digital, analog, and mixed signal circuits, including built-in self-test, delay fault testing, online test and 2.5D/3D circuits. 3. Design For Testability DFT for modern ICs, including FPGAs, SoCs, NoCs, GPUs, ASICs, low-power designs, and RISC-V designs. 4. Error Detection, Correction, and Recovery Robust error handling strategies, including error-control coding, fault masking, and recovery schemes, using hardware/software techniques and architectural approaches. 5. Dependability Analysis and Validation Rigorous evaluation of system dependability, employing fault injection, cross-layer reliability analysis, and AI/ML-based methods. 6. Repair, Restructuring and Reconfiguration Dynamic adaptation techniques for fault tolerance and resilience, including self-healing reconfigurable circuits, and on-line repair. 7. Defect and Fault Tolerance Design of reliable systems in the presence of defects and faults, design space exploration for dependable systems, in critical applications and addressing transient/soft faults. 8. Aging and Radiation effects Radiation effects, radiation-induced errors in nano-technologies, modeling radiation environments, development of novel radiation test and simulation techniques and developing radiation hardened designs. 9. Aging and Lifetime Reliability Understanding aging mechanisms, designing for long-term reliability, and managing thermal and variability challenges. 10. Emerging Technologies Error management strategies for quantum computing, memristive devices, spintronics, microfluidics, and approximate computing. 11. RISC-V Use of open ISAs in dependable and security applications. 12. Design for Security Protecting ICs against fault attacks, hardware trojans, and other security threats, the interplay between security, reliability, and trust. 13. Dependable Applications and Case Studies Real world applications of dependability techniques in 2.5D/3D ICs, IoT, automotive, aerospace, autonomous systems, and AI systems. 14. Sustainability and Green EEE Highlight the need for energy-efficient and environmentally friendly EEE designs, including low-power design techniques and green manufacturing processes.
由 Dou Sun 最后更新于

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