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CICC 2015: IEEE Custom Integrated Circuits Conference

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截稿日期:
2015-05-04 Extended
通知日期:
会议日期:
2015-09-28
会议地点:
San Jose, California, USA
QUALIS: B2   浏览: 25480   关注: 6   参加: 0

会伴指数 (CP-I)

50.6 / 100
全站第 1,434 名 / 共 5,683 个会议 · 前 26%

电气与电子工程 第 76 / 509

学术认可 (35%)
68
投稿选择性 (20%) 无数据 —— 按中性基准 50 分计入 —
会议传承 (20%) 无数据 —— 按中性基准 50 分计入 —
社区关注 (10%)
31
资料公开度 (15%)
25

用到的输入: 收录等级：QUALIS B2 · 在会伴关注它的研究者：6 人 · 过去 24 个月打开过本页的研究者：4 人

公开资料里还缺: 历年录用率 (+4.5) · 历届信息 (+3.0) · 最佳论文记录 (+2.3)
主办方认领本会议后，可直接在这一页补上；分数每晚重算。如何提升这个分数

置信度 60% —— 分数中有多大比例来自实际观测到的数据，而不是中性基准。 这个分数是怎么算出来的 · 查看完整榜单 · 算法版本 1.1 · 算于 2026-09-21

征稿

CICC 2015 (IEEE Custom Integrated Circuits Conference) is a QUALIS B2 conference held in San Jose, California, USA on 2015-09-28. The paper submission deadline is 2015-05-04 (extended).

The IEEE Custom Integrated Circuits Conference (CICC) is the premier conference devoted to IC development. CICC showcases original, first-published innovative analog and digital circuit techniques covering a broad spectrum of technical topics. It is a forum for circuit, IC and SoC designers, CAD developers, manufacturers and ASIC users. CICC is the conference to find out how to solve design problems and improve circuit design and chip design techniques. Conference Highlights Technical Papers Education on new, state-of-the-art developments is the core of the CICC technical program. Over 160 papers, addressing a broad range of circuits, applications, design techniques, tools, test, reliability, and system-on-a-chip, will be presented. Awards for Best Paper will be given in both the regular and student submission categories. Top-rated CICC papers are also eligible to be considered for publication in a special issue of the IEEE Journal of Solid State Circuits. Poster Presentations CICC will include poster presentations as well as traditional lecture presentations. Poster presentations are a unique opportunity for a greater depth of discussion between authors and the CICC audience. Panels Leaders from the IC industry debate key issues and controversial topics in panel sessions. CICC panels are well known for their lively and thought-provoking discussion and audience participation. Educational Sessions Educational sessions are included in the conference fee and strategically placed so that the attendees can get a basic understanding of the topics before going more in depth with the technical papers. These tutorials, instructed by recognized invited speakers, are among the best in the industry. They are valuable opportunities to refresh key skills in traditional circuit-design methods and acquire knowledge in vital new areas in analog, digital, and RF integrated circuit IC design. Exhibits Semiconductor manufacturers, software tool suppliers, silicon IP providers, design-service houses, and technical book publishers offer displays and demonstrations of their products. Conference Events Our Welcome Reception, Conference Reception and Conference Luncheon complement the technical program of CICC and provide additional opportunities for discussion and peer networking in a relaxed environment. The Poster Presentations will also be a major conference event, attended by all and accompanied by food and beverage. CICC presents papers in the following areas: Analog Circuit Design: Data Converters, Nyquist and oversampled, mixed signal analog/digital applications, analog sensor processing applications, low voltage and low power analog, deep submicron issues in analog design. Blocks for analog systems amplifiers, sample holds, voltage references and regulators, filters continuous and discrete, non linear analog blocks, novel clock generation. Data Converters: Nyquist A/D and D/A converters; oversampling converters (continuous time and sampled), novel A/D and D/A architectures and directions, compressive sensing, application-specific converter techniques (ultralow power, radiation hard, high voltage / high power). Systems on Chip and 3D: Architectures, micro-architectures, methodologies and infrastructures for SoC or multi-dimensional designs realized in silicon. Design challenges and solutions in advanced process nodes. General purpose or application specific 3D / 2.5D multi-chip designs. Innovative, advanced, complex or high performance circuits or design techniques for digital or mixed signal SoCs, ASICs or FPGAs. Memory: Circuits, architectures, device technologies, and manufacturing solutions addressing all memory aspects such as power-performance-density trade-offs, Vmin, resiliency, endurance, data retention, process variations, and reliability. Of interest are both mainstream and emerging memories including but not limited to SRAM, CAM, ROM, DRAM, Flash, MRAM, RRAM, PCM, OTP, and 3D memories used in consumer electronics as well as novel applications. Biomedical, Actuators, MEMS, and Sensors: Advanced ICs for biomedical, aerospace, automotive, energy, environment, and security applications. Ultra�low power circuits for emerging technologies in medicine, actuators, MEMS, and Internet�of�Things (IoT) sensors are of particular interest. Examples include biomedical sensors, microchemical and image sensors, next�generation sequencing, micro and nanofluidic chips, novel displays, organic and flexible electronics, energy harvesting, and implantables. IC Manufacturing: Special focus on challenges of and alternatives to CMOS scaling, Design for Manufacturability, specialty manufacturing techniques, and design / technology interaction. Advanced manufacturing techniques using any combination of bulk/SOI CMOS, non-silicon, and photonic technologies. Evolving chip packaging such as chip stacking, lead-free, flip-chip, and System-in-Package. Tutorial content and impact to the design community is encouraged. Power Management: Circuit and system architectures for power management and conversion. Advanced circuit topologies for switching / linear regulators and innovations in energy scavenging, wireless and peripheral charging, battery metering, control methodologies, and other topical areas related to advances in power generation, distribution, and conversion. Simulation and Modeling: Simulation/modeling techniques and methodologies for device-and circuit-level analysis, design and verification of analog, RF, memory, and mixed-signal circuits. Statistical and reliability modeling and simulation. Effects of FinFETs and FD-SOI on circuit level performance and variability. Compact models for active and passive devices. Behavioral modeling and simulation. PDK generation and validation. Parasitic extraction and reduction. Modeling and simulation of 3D ICs. Signal-integrity modeling and simulation. Package modeling. Test, Debug, and Reliability: Debug techniques. DFT (design for test) for digital/analog/mixed-signal circuits, memory, equalizers, CDR, high speed I/O, MEMS, RF, 2.5D/3D, and photonic ICs. Design techniques for extremely reliable applications. Reliability concerns in leading edge technologies, such as soft errors and aging issues. Innovations in ESD protection. Issues of testability and constraints due to protection of intellectual property or system security. Wireline Communications: Circuits and systems for electrical and optical communications, including: serial links, backplanes, high-speed memory and graphics interfaces, intra-chip and chip-to-chip interconnects, peripheral I/O buses, photonic transceivers; circuit blocks including serializers, deserializers, equalizers, link-related clocking (PLL, DLL, and CDR), electro-optical conversion (TIA, laser/modulator drivers). Wireless Designs: Integrated wireless transceiver architectures and sub-circuits for cellular, connectivity, MIMO, broadband and low-power communication, Millimeter-Wave and Terahertz (radar, sensing and imaging), Wireless Sensor Networks and IoT. Papers on RF circuit solutions targeting emerging wireless applications (5G, WLAN 802.11ac/ad/af/ah/ax, LTE Advanced) are particularly encouraged.
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