Conference Information

HOST 2027: IEEE International Symposium on Hardware-Oriented Security and Trust

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Submission Date:
2026-11-01 Due in 18 days
Notification Date:
2027-02-09
Conference Date:
2027-05-03
Location:
Washington DC, USA
Years:
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Conference Partner Index (CP-I)

54.5 / 100
Ranked #911 of 5,696 conferences · Top 16%

#71 of 362 in Security & Privacy

Academic recognition (35%) No data - scored at the neutral baseline of 50 —
Submission selectivity (20%) No data - scored at the neutral baseline of 50 —
Editions held (20%)
82
Community attention (10%)
24
Public record completeness (15%)
55

Inputs used: Editions on record: 20 · Researchers following it here: 1 · Researchers who opened this page in the past 24 months: 9

Missing from the public record: Historical acceptance rates (+4.5) · Best-paper records (+2.3)
Organizers can add these from this page after claiming the conference; scores are recomputed nightly. How to raise this score

Confidence 45% - the share of the score backed by observed data rather than the neutral baseline. How this score is calculated · Browse the ranking · Algorithm version 1.1 · Computed 2026-10-13

Call For Papers

HOST 2027 (IEEE International Symposium on Hardware-Oriented Security and Trust) is an academic conference held in Washington DC, USA on 2027-05-03. The paper submission deadline is 2026-11-01. Acceptance notifications are sent on 2027-02-09.

IEEE International Symposium on Hardware Oriented Security and Trust (HOST) – the premier event aiming to facilitate the rapid growth of hardware security research and development – has opened the call for contributions. The 20th HOST will be held in May 2027 at Washington, DC. HOST 2027 invites original contributions in all areas of hardware and security, including but not limited to: AI and Hardware Security: e.g., AI for hardware security enforcement or finding hardware vulnerabilities, hardware security for AI models, new security principles for trustworthy AI Computer-aided Design (CAD) for Hardware Security Verification: e.g., design-time verification, testing, and metrics for hardware security across the lifecycle. Hardware Security Primitives: e.g., PUFs, TRNGs, cryptography, post-quantum cryptography, hardware meters. Hardware Attack and Defense: e.g., hardware Trojans, fault injection, side-channels, hardware reverse engineering, hardware obfuscation. Architecture Security: e.g., architectural side-channels, trusted execution environment, FPGA, and reconfigurable fabric security. System Security: e.g., SoC/IP security, CPS/IoT security, sensor network security, smart grid security, cloud security, secure boot, attestation and device provisioning, provenance, hardware–software co-design for security, trusted update mechanisms. Chiplet, Packaging, and Heterogeneous Integration Security: e.g. advanced packaging security, chiplet/interposer trust, die-to-die interfaces, 2.5D/3D integration. Emerging Security and Privacy Threats and Solutions: e.g., privacy-enhancing architecture, blockchain, quantum platforms, cryptocurrency security, and hardware/system security topics.
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