The HPC ASIA 2025 consists of 5 Tracks:

    HPC Applications, Parallel Computing & Systems Software
        High-performance computing applications
        Parallel computing algorithms and techniques
        Systems software for HPC
        Hybrid and heterogeneous computing systems
        Fault-tolerant computing
        Scalability and efficiency in HPC systems
        Cloud computing for HPC
    Data, Storage, Visualization
        Big data processing and analytics
        Distributed and parallel file systems
        Storage architectures and systems
        Data visualization techniques
        Data provenance and traceability
        High-performance I/O and storage optimization
        Visualization and image processing in HP
    Machine Learning, AI, and Emerging Technologies
        Machine learning algorithms and applications
        Deep learning techniques and frameworks
        AI integration in HPC
        Emerging technologies (quantum computing, neuromorphic computing, etc.)
        AI ethics and bias
        AI-driven data analytics
        Real-world AI applications in various industries
        Future trends in AI and emerging technologies
    Performance Modeling, Evaluation, and Analysis
        Performance modeling and prediction
        Benchmarking and performance evaluation
        Scalability analysis
        Tools and methodologies for performance analysis
        Performance optimization techniques
        Case studies on performance improvements
        Power and energy efficiency in performance modeling
        Real-world application performance analysis
    Processor, Accelerator, Network Architecture
        Processor architecture advancements
        Accelerator technologies (GPUs, FPGAs, ASICs)
        Network architecture and interconnects
        Memory hierarchy and management
        Energy-efficient processor and accelerator design
        Dependable and fault-tolerant architectures
        Emerging processor and network technologies
        Integration of new technologies in processor and network design