会议信息

ASYNC 2020: IEEE International Symposium on Asynchronous Circuits and Systems

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ASYNC
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截稿日期:
2020-01-06 Extended
通知日期:
2020-02-20
会议日期:
2020-05-17
会议地点:
Snowbird, Utah, USA
届数:
26
浏览: 18052   关注: 0   参加: 0

会伴指数 (CP-I)

50.0 / 100
全站第 1,597 名 / 共 5,693 个会议 · 前 29%

电气与电子工程 第 94 / 511

学术认可 (35%) 无数据 —— 按中性基准 50 分计入 —
投稿选择性 (20%) 无数据 —— 按中性基准 50 分计入 —
会议传承 (20%)
89
社区关注 (10%)
10
资料公开度 (15%)
25

用到的输入: 有据可查的届次：26 · 过去 24 个月打开过本页的研究者：3 人

公开资料里还缺: 历年录用率 (+4.5) · 历届信息 (+3.0) · 最佳论文记录 (+2.3)
主办方认领本会议后，可直接在这一页补上；分数每晚重算。如何提升这个分数

置信度 45% —— 分数中有多大比例来自实际观测到的数据，而不是中性基准。 这个分数是怎么算出来的 · 查看完整榜单 · 算法版本 1.1 · 算于 2026-10-05

征稿

ASYNC 2020 (IEEE International Symposium on Asynchronous Circuits and Systems) is an academic conference held in Snowbird, Utah, USA on 2020-05-17. The paper submission deadline is 2020-01-06 (extended). Acceptance notifications are sent on 2020-02-20.

The International Symposium on Asynchronous Circuits and Systems (ASYNC) is the premier forum for researchers to present their latest findings in the area of asynchronous design. Besides a regular paper track, the conference will also hold a special industrial papers track and a fresh ideas workshop. Top rated ASYNC 2020 papers will be invited to a special issue on Self-Timed Computing in Royal Society Philosophical Transactions. REGULAR PAPERS: Authors are invited to submit papers on any aspect of asynchronous design, ranging from design, synthesis, and test, to asynchronous applications in system-level integration and emerging computing technologies. Topics of interest include: Mixed-timed circuits, GALS systems, networks-on-chips, multi-chip interconnects, and 3D integration; Elastic and latency-tolerant synchronous design; Asynchronous pipelines, architectures, CPUs, and memories; Asynchronous logic in ultra-low power and power-constrained systems, energy harvesting and mixed-signal/analog design; Asynchrony in emerging technologies, such as bio, nano, and quantum computing; CAD tools for asynchronous design, synthesis, analysis, and optimization; Formal methods for verification and performance/power analysis; Test, security, fault tolerance, and radiation-hard design; Asynchronous variability-tolerant, resilient design and design for manufacturing; Asynchronous design for neural networks and machine learning applications; Circuit designs, case studies, comparisons, and applications. Hardware implementations of asynchronous models and algorithms, asynchronous techniques in clocked designs, and elastic and latency-tolerant synchronous design Submissions must report original scientific work, in 6-8 pages IEEE double-column conference format, with author information concealed. Authors who feel that extra pages are absolutely required to obtain top quality of their article may contact the Program Chairs. Accepted papers will be published in the IEEE digital library IEEEXplore and symposium proceedings. INDUSTRIAL PAPERS: ASYNC 2020 will include a special industrial workshop with papers from industry on the state-of-the-art application of asynchronous designs to both existing and emerging technologies. We solicit 1- to 2-page submissions, using IEEE double-column conference format. These papers will go through a separate light-weight review process. Accepted papers will be published in the IEEE digital library IEEEXplore and symposium proceedings. The submission deadline will be Feb 14, 2020 . FRESH IDEAS AND EMERGING HOT TOPICS WORKSHOP: ASYNC 2020 will accommodate a special workshop to present “fresh ideas” in asynchronous design, that are not yet ready for publication as well as “emerging hot topics” to describe emerging areas of interest for asynchronous designs. We solicit 1-to-2-page submissions for the workshop, which will go through a separate light-weight review process. Accepted submissions will be handed out at the workshop. The submission deadline will be Feb 27, 2020.
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