Conference Information
IWoDA 2020: International Workshop on Design Automation
http://www.iwoda.org/
Submission Date:
2019-12-05
Notification Date:
Conference Date:
2020-10-16
Location:
Madrid, Spain
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Conference Location
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Call For Papers
We invite submissions on a wide range of research topics, spanning both theoretical and systems research. The topics of interest include, but are not limited to:

2D, 3D   on-chip power delivery, network analysis and optimization
Hardware and Software co-design,   co-simulation and co-verification
Advanced multimedia   application
Hardware for large-scale data analytics and processing
Analog and mixed-signal   modeling and simulation techniques
Hardware Security
Analog and mixed-signal RF   synthesis
High-frequency electromagnetic simulation of circuit
Analog and mixed-signal RF   test
High-level synthesis tool and methodology
Analog Design, Simulation,   Verification and Test
Human-computer interface
Analog layout, verification   and simulation techniques
In-Package and On-Chip Communication
Analysis and optimization
Intellectual property (IP) core and platform-based SoC design
Architectural low-power design   technique
Inter and intra -chip interconnect, network and interface
Architecture, tool and   methodology for secure hardware
Interconnect planning and synthesis
Architectures for machine   learning and artificial intelligence
Kernel, middleware and virtual machine
Artificial intelligence   hardware and systems
Lithography and DFM
Automatic test pattern   generation
Logic synthesis and physical design technique for FPGA
Automotive system design and   optimization
Low-power design and methodology
Autonomous Systems   Architectures
Machine Learning and Artificial Intelligence Architectures
Autonomous Systems Design   Tools and Methodologies
Manufacturing Test and Reliability
Autonomous Systems Safety and   Reliability
Memory test and repair
Big data application
Mixed-signal design consideration
Biochip and biodata processing
Model- and component-based embedded system and software design
Biomedical application
Multi-core SoC architecture
Built-in self-test
Near-Memory and In-Memory Computing
CAD for memory circuits
Networks-on-Chip
CAD for nanotechnology, MEMS,   3D IC, quantum computing
Networks-on-chip and NoC-based system design
Circuit-level formal   verification
Neuromorphic and brain-inspired computing
Clock network synthesis
New transistor, device and process technology
Combinational, sequential and   asynchronous logic synthesis
Noise analysis
Communication traffic and   modeling
Online test and fault tolerance
Communication-centric system   design, application and simulation
Optical or photonic interconnect and network
Compiler and toolchain
Package, PCB and 3D-IC routing
Cross-Layer Power Analysis and   Low-Power Design
Performance analysis and optimization
Cross-layer security
Physical Design and Verification
Cyber physical system
Placement and routing optimization
Cyber-physical systems and   Internet-of-Things platforms
Post layout and post-silicon optimization
Cyber-physical systems and IoT   security
Power modeling, analysis and simulation
Dependable architecture
Power-aware analog circuit and system design
Design for manufacturability,   yield and defect tolerance
Power, ground and package modeling
Design for reliability, aging   and robustness
Rack-scale interconnect and network
Design for security and   security primitive
Real-time system
Design for testing
Reconfigurable and self-adaptive SoC architecture
Design methodology for mobile   and wearable devices
Reconfigurable Architectures
Design of Cyber-physical   Systems and IoT
Reliability, aging and soft error analysis
Design Verification and   Validation
Resilience under manufacturing variation
Deterministic and statistical   timing
Resource allocation for heterogeneous computing platform
Device and circuit-level   simulation tool and methodology
Reticle enhancement, lithography-related design and   optimization
Device, circuit and   interconnect modeling and analysis
RTL and gate-leveling modeling, simulation and verification
Digital and Analog Circuits
RTL and Logic Level and High-level Synthesis 
Digital Design
Security modeling and analysis
Domain-specific architecture
Security vulnerabilities in artificial intelligence
Domain-specific embedded   libraries
Signal and power integrity
Electromagnetic (EM) modeling   and analysis
Spintronic, phase-change, single-electron
Electromobility
Storage software and application
Embedded and Cross-Layer   Security
Storage system and memory architecture
Embedded Memory, Storage and   Networking
System on Chip (SoC), Heterogeneous architectures
Embedded Software
System test and 3D IC test
Embedded System
System verification and analysis
Emerging Device Technologies
System-level design exploration, synthesis and optimization
Emerging interconnect   technology and application
System-level formal verification
Emerging models of computation
System-level modeling, simulation, validation tools and   methodology
Energy harvesting and battery   management
System-on-Chip Design Methodology
Energy-storage, smart-grid and   smart-building design and optimization
Technology mapping
Extraction, TSV and package   modeling
Thermal aware design
Fault analysis, detect and   tolerance
Time-Critical System Design
Fault modeling and simulation
Timing and Simulation
Floorplanning, partitioning   and placement
Validation of cognitive systems
Last updated by Dou Sun in 2019-11-12
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